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    MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS
    21.
    发明申请
    MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS 审中-公开
    具有独立尺寸元素的存储单元

    公开(公告)号：US20150028280A1

    公开(公告)日：2015-01-29

    申请号：US13952357

    申请日：2013-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Samuele Sciarrillo ,  Marcello Ravasio

    IPC: H01L45/00

    Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

    Abstract translation: 提供了存储单元结构及其形成方法。 示例性存储单元可以包括开关元件和与开关元件串联形成的存储元件。 开关元件的最小横向尺寸不同于存储元件的最小横向尺寸。

    Cross-point memory and methods for fabrication of same
    23.
    发明授权
    Cross-point memory and methods for fabrication of same 有权

    公开(公告)号：US10367033B2

    公开(公告)日：2019-07-30

    申请号：US16112570

    申请日：2018-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Ombretta Donghi ,  Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    24.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 审中-公开

    公开(公告)号：US20190013359A1

    公开(公告)日：2019-01-10

    申请号：US16112476

    申请日：2018-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Samuele Sciarrillo

    IPC: H01L27/24 ,  H01L45/00

    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

    Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical polishing (CMP) process
    26.
    发明授权
    Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical polishing (CMP) process 有权
    通过两步化学机械抛光（CMP）工艺在存储器单元中形成顶部电极之间的互连的方法

    公开(公告)号：US09443763B2

    公开(公告)日：2016-09-13

    申请号：US14025537

    申请日：2013-09-12

    Applicant: Micron Technology, Inc.

    Inventor： Samuele Sciarrillo

    IPC: H01L21/768 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L21/76895 ,  H01L21/7684 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.

    Abstract translation: 提供了存储单元阵列结构及其形成方法。 用于形成存储器单元阵列的示例性方法可以包括形成多个垂直结构，每个垂直结构具有与顶部电极串联的存储元件串联的开关元件，以及在多个的各个顶部电极之间形成互连导电材料 的垂直结构。 互连导电材料经过回蚀和化学机械抛光（CMPed）。 在互连导电材料CMP之后，在互连导电材料上形成导线。

    Cross-point memory and methods for fabrication of same
    30.
    发明授权
    Cross-point memory and methods for fabrication of same 有权

    公开(公告)号：US11011579B2

    公开(公告)日：2021-05-18

    申请号：US16112476

    申请日：2018-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Samuele Sciarrillo

    IPC: H01L27/24 ,  H01L45/00

    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

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