公开(公告)号：US11100972B2

公开(公告)日：2021-08-24

申请号：US16786725

申请日：2020-02-10

Applicant: Micron Technology, inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C11/406

Abstract: Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.

公开(公告)号：US20210209039A1

公开(公告)日：2021-07-08

申请号：US17207561

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3206

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US10657081B2

公开(公告)日：2020-05-19

申请号：US16014498

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G11C5/14 ,  G06F13/16 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3206

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US20190065416A1

公开(公告)日：2019-02-28

申请号：US16014498

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F1/32 ,  G06F5/06

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US12243607B2

公开(公告)日：2025-03-04

申请号：US18392487

申请日：2023-12-21

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/46 ,  G11C7/10 ,  G11C29/12 ,  G11C29/44

Abstract: Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.

公开(公告)号：US12189974B2

公开(公告)日：2025-01-07

申请号：US17345267

申请日：2021-06-11

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd J. Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Mark D. Ingram

IPC: G06F3/06 ,  G06F1/06

Abstract: Methods, systems, and devices for operational monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a memory device may include components configured for monitoring health or life expectancy or both of the memory device, such as components internal to the memory device that identify and store various indications of a duration of operating a memory device. An operational duration stored at the memory device may be used in various operations, such as calculations or comparisons, to evaluate health or life expectancy of the memory device, which may include or be supported by various signaling with a host device.

公开(公告)号：US20240412801A1

公开(公告)日：2024-12-12

申请号：US18742749

申请日：2024-06-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C29/42 ,  G11C8/18 ,  G11C29/12 ,  G11C29/14

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

公开(公告)号：US12154639B2

公开(公告)日：2024-11-26

申请号：US17851721

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/04

Abstract: Methods, systems, and devices for memory fault notification are described. A memory device may receive a configuration corresponding to a circuit node of the memory device, where the circuit node may be selectively coupled with a set of resistors. The memory device may determine a fault condition and couple the circuit node to at least a first resistor based on determining the fault condition. The memory device may bias the circuit node to a first voltage value that satisfies a voltage threshold based on coupling the circuit node to the first resistor. The memory device may output an indication of a fault state to notify a host device that a fault has been detected.

公开(公告)号：US12081235B2

公开(公告)日：2024-09-03

申请号：US18098995

申请日：2023-01-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/43

CPC classification number: H03M13/1111 ,  H03M13/43 ,  H03M13/611

Abstract: Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.

公开(公告)号：US20240282400A1

公开(公告)日：2024-08-22

申请号：US18443948

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Paul A. Laberge

IPC: G11C29/52

CPC classification number: G11C29/52

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may identify a fault type (e.g., recoverable or unrecoverable) based on a fault signature associated with a given characteristic of the read strobe signal. The host device may perform recovery operations based on the fault type identified.