公开(公告)号：US20230206985A1

公开(公告)日：2023-06-29

申请号：US17563878

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kiyoshi Nakai ,  Seiji Narui

IPC: G11C11/4076 ,  G11C11/4096 ,  H01L25/065

CPC classification number: G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.

公开(公告)号：US20210225848A1

公开(公告)日：2021-07-22

申请号：US17202144

申请日：2021-03-15

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Yuki Ebihara

IPC: H01L27/108 ,  G11C11/4074 ,  G11C19/08 ,  G11C19/28 ,  G06F5/06

Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

公开(公告)号：US10943622B2

公开(公告)日：2021-03-09

申请号：US17020712

申请日：2020-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiji Narui

IPC: G11C5/06 ,  G11C7/10 ,  H01L27/108 ,  H01L25/065

Abstract: An example apparatus includes: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips including first and second memory chips; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.

公开(公告)号：US10777232B2

公开(公告)日：2020-09-15

申请号：US16267115

申请日：2019-02-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiji Narui

IPC: G11C5/06 ,  G11C7/10 ,  H01L25/065 ,  H01L27/108

Abstract: An apparatus that includes: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips including first and second memory chips; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.

公开(公告)号：US20180151207A1

公开(公告)日：2018-05-31

申请号：US15365563

申请日：2016-11-30

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C8/18 ,  G11C7/10 ,  G11C19/28

CPC classification number: G11C7/1087 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C19/28 ,  G11C2207/108 ,  G11C2207/2272

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US09472253B2

公开(公告)日：2016-10-18

申请号：US14607858

申请日：2015-01-28

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Chikara Kondo

IPC: G11C7/22 ,  G11C5/02 ,  G11C7/10 ,  H01L25/065 ,  G11C5/06 ,  G11C11/4097

CPC classification number: G11C7/22 ,  G11C5/02 ,  G11C5/063 ,  G11C7/10 ,  G11C11/4097 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.

Abstract translation: 本公开中公开的半导体器件包括形成在半导体衬底的第一表面上的第一端子，形成在与第一表面相对的半导体衬底的第二表面上方的第二端子，穿过半导体的第一贯穿衬底通孔（TSV） 基板和先进先出（FIFO）电路，其中第一TSV和FIFO电路串联耦合在第一端子和第二端子之间。

公开(公告)号：US11854601B2

公开(公告)日：2023-12-26

申请号：US17563878

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kiyoshi Nakai ,  Seiji Narui

IPC: G11C11/4076 ,  H01L25/065 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.

公开(公告)号：US20210264955A1

公开(公告)日：2021-08-26

申请号：US17316140

申请日：2021-05-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiji Narui

IPC: G11C5/02 ,  H01L25/065 ,  G11C5/04 ,  H01L27/105

Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.

公开(公告)号：US10964702B2

公开(公告)日：2021-03-30

申请号：US16163471

申请日：2018-10-17

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Yuki Ebihara

IPC: G06F5/06 ,  H01L27/108 ,  G11C11/4074 ,  G11C19/08 ,  G11C19/28

Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

公开(公告)号：US10943625B2

公开(公告)日：2021-03-09

申请号：US16721515

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C7/10 ,  G11C19/28 ,  G11C7/22 ,  G11C16/32

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.