公开(公告)号：US20230328975A1

公开(公告)日：2023-10-12

申请号：US18207499

申请日：2023-06-08

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Indra V. Chary

IPC: H10B41/40 ,  H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11785775B2

公开(公告)日：2023-10-10

申请号：US17153740

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Shuangqiang Luo ,  Harsh Narendrakumar Jain ,  Nancy M. Lomeli ,  Christopher J. Larsen

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/562 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

公开(公告)号：US11715685B2

公开(公告)日：2023-08-01

申请号：US17064453

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Nancy M. Lomeli ,  Xiao Li

IPC: H01L23/522 ,  G11C16/08 ,  G11C16/24 ,  H01L21/768 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5226 ,  G11C16/08 ,  G11C16/24 ,  H01L21/76831 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

公开(公告)号：US20230137958A1

公开(公告)日：2023-05-04

申请号：US17517355

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Nancy M. Lomeli ,  Rui Zhang

IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

Abstract: Memory circuitry comprising strings of memory cells comprising laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from the memory-array region into a stair-step region. Individual stairs in the stair-step region comprise one of the conductive tiers and a riser. Conductive vias are individually directly against conductive material that is in the one conductive tier in one of the individual stairs. Individual of the conductive vias where directly against the conductive material are horizontally-longitudinally-elongated at an angle of 0° to 60° horizontally from the riser of the one individual stair. Other embodiments, including method, are disclosed.

公开(公告)号：US11605642B2

公开(公告)日：2023-03-14

申请号：US17124313

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20230045353A1

公开(公告)日：2023-02-09

申请号：US17396939

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Indra V. Chary ,  Anilkumar Chandolu ,  Sidhartha Gupta ,  Shuangqiang Luo

IPC: H01L23/528 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11524 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

公开(公告)号：US20220406712A1

公开(公告)日：2022-12-22

申请号：US17349158

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Shuangqiang Luo ,  Lifang Xu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A microelectronic device comprises a stack structure, contact structures, and additional contact structures. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure is divided into blocks each comprising a stadium structure including steps comprising horizontal ends of the tiers. The contact structures are within a horizontal area of the stadium structure and vertically extend through the stack structure. The additional contact structures are on at least some of the steps of the stadium structure and are coupled to the contact structures. Memory devices and electronic devices are also disclosed.

公开(公告)号：US20220336487A1

公开(公告)日：2022-10-20

申请号：US17301915

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Ching-Huang Lu ,  Shuangqiang Luo

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: An electronic device comprising first blocks and second blocks of an array comprising memory cells. The memory cells in the first and second blocks comprise memory pillars extending through a stack. The memory pillars comprise a charge blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge blocking material, a tunnel dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunnel dielectric material, and a fill material between opposing sides of the channel material. One or more of the storage nitride material and the tunnel dielectric material in the first blocks differ in thickness or in material composition from one or more of the storage nitride material and the tunnel dielectric material in the second blocks. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20220108947A1

公开(公告)日：2022-04-07

申请号：US17064453

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Nancy M. Lomeli ,  Xiao Li

IPC: H01L23/522 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/768

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

公开(公告)号：US11183456B2

公开(公告)日：2021-11-23

申请号：US16743329

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Shuangqiang Luo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.