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公开(公告)号：US20140092701A1
公开(公告)日：2014-04-03
申请号：US14099294
申请日：2013-12-06
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm
IPC: G11C8/18
CPC classification number: G11C8/18
Abstract: Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed.
Abstract translation: 公开了用于在堆叠中的管芯中产生时钟信号并且在堆叠中的另一管芯中接收时钟信号的装置，系统和方法。 公开了附加装置，系统和方法。
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公开(公告)号：US20130314131A1
公开(公告)日：2013-11-28
申请号：US13957333
申请日：2013-08-01
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm
IPC: H03L7/081
CPC classification number: H03L7/0818 , H03K5/133 , H03K5/14 , H03L7/0814 , H03L7/089
Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.
Abstract translation: 公开了锁定环路，延迟线路，延迟电路和用于延迟信号的方法。 示例延迟电路包括包括多个延迟级的延迟线，每个延迟级具有输入并且还具有单个反相延迟器件，并且还包括耦合到延迟线的两相出口树，并且被配置为提供第一和 第二输出时钟信号响应于来自多个延迟级的延迟级的输入的时钟信号。 另一示例延迟电路包括被配置为提供多个延迟的时钟信号的延迟线，每个延迟的时钟信号相对于等于单个反相延迟器件的延迟的先前延迟的时钟信号具有延迟。 示例延迟电路还包括被配置为响应延迟的时钟信号提供第一和第二输出时钟信号的两相出口树。
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公开(公告)号：US20130039144A1
公开(公告)日：2013-02-14
申请号：US13652108
申请日：2012-10-15
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm
IPC: G11C8/18
CPC classification number: G11C8/18
Abstract: Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US12154645B2
公开(公告)日：2024-11-26
申请号：US18363587
申请日：2023-08-01
Applicant: Micron Technology, Inc.
Inventor： Linh H. Nguyen , Diana C. Majerus , Tyler J. Gomm
Abstract: Pulse detection in microelectronic devices, and related methods, devices, and systems, are described herein. A device may detect and compare a number of pulses of a signal to a timing aperture to determine if any of the number of pulses is unacceptable. The timing aperture, which may be based on a timing signal and/or one or more pulse width thresholds, may define an acceptable pulse versus an unacceptable pulse.
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公开(公告)号：US20230268927A1
公开(公告)日：2023-08-24
申请号：US17677724
申请日：2022-02-22
Applicant: Micron Technology, Inc.
Inventor： Eric A. Becker , Tyler J. Gomm
CPC classification number: H03M1/0617 , H03K3/0315 , H03M7/165 , G04F10/005
Abstract: A time to digital circuit may provide a time measurement of an event, or a time measurement of a duration between multiple events. Various electronic devices may include one or more time to digital circuits. A time to digital circuit may include circuitry to use Thermometer Code for measuring the duration of the time. For example, the time to digital circuit may generate alternating signals using a ring oscillator when receiving an indication of an event. Moreover, the time to digital circuit may convert the alternating signals to a consistent signal with only one transition between high and low signals in multiple consecutive signals. Furthermore, the time to digital circuit may correct erroneous signal values of the consistent signals when multiple transitions between high and low signals in multiple consecutive signals occurs.
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Patent Agency Ranking
公开(公告)号：US11515860B2
公开(公告)日：2022-11-29
申请号：US17198925
申请日：2021-03-11
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm
Abstract: A jitter generator may include a duty cycle code generator that generates a duty cycle control signal and an input buffer that outputs a signal based on its duty cycle. The input buffer may be coupled to the duty cycle code generator and to a source of a clock signal. After receiving the clock signal, the input buffer outputs the clock signal having jitter relative to the clock signal received from the source. The jitter may be added at least in part by components of the input buffer offsetting different transitions of the clock signal according to the duty cycle. Jitter may be added when the duty cycle changes in response to changes in the duty cycle control signal, such as in response to number generator circuitry of the duty cycle code generator update its output number, in response to a mode change received from a controller, or the like.
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公开(公告)号：US10438648B2
公开(公告)日：2019-10-08
申请号：US15868232
申请日：2018-01-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasuo Satoh , Tyler J. Gomm
Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.
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28.发明申请公开(公告)号：US20190207592A1
公开(公告)日：2019-07-04
申请号：US16294640
申请日：2019-03-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm , Yasuo Satoh
IPC: H03K3/037
CPC classification number: H03K3/0372 , G11C7/106 , G11C7/222 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/4093 , H03K3/017 , H03K19/20
Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
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29.发明申请公开(公告)号：US20190097613A1
公开(公告)日：2019-03-28
申请号：US15717610
申请日：2017-09-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm , Yasuo Satoh
IPC: H03K3/037
Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
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公开(公告)号：US09124253B2
公开(公告)日：2015-09-01
申请号：US14058092
申请日：2013-10-18
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm , Yasuo Satoh
CPC classification number: H03K3/017 , H03K5/1565 , H03L7/06
Abstract: Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit configured to generate a complementary signal responsive to an input signal. The complement generation circuit is configured to operate in a first voltage domain. The apparatus also includes a compensation circuit configured to generate a compensated signal by compensating the input signal for a delay corresponding to the complement generation circuit. The compensation circuit is configured to operate in a second voltage domain. The apparatus also includes a phase mixing circuit configured to combine the complementary signal and the compensated signal to generate an output signal.
Abstract translation: 公开了用于在电压域边界处保持占空比的方法和装置。 一个示例性装置包括补码生成电路，其被配置为响应于输入信号产生互补信号。 补码生成电路被配置为在第一电压域中操作。 该装置还包括补偿电路，其被配置为通过对与补码生成电路相对应的延迟补偿输入信号来产生补偿信号。 补偿电路被配置为在第二电压域中操作。 该装置还包括相位混合电路，该相位混合电路被配置为组合互补信号和经补偿的信号以产生输出信号。
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