公开(公告)号：US11742017B2

公开(公告)日：2023-08-29

申请号：US17700346

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: G11C11/4076 ,  H03L7/081 ,  H03K5/14 ,  H03K5/131 ,  H03K5/00

CPC classification number: G11C11/4076 ,  H03K5/131 ,  H03K5/14 ,  H03L7/0814 ,  H03L7/0818 ,  H03K2005/00019 ,  H03K2005/00241

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.

公开(公告)号：US20220301610A1

公开(公告)日：2022-09-22

申请号：US17204063

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He ,  Hyunui Lee

IPC: G11C8/08 ,  G11C5/14 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

公开(公告)号：US11049543B2

公开(公告)日：2021-06-29

申请号：US16559344

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Yasuo Satoh ,  Kenji Mae

IPC: G11C7/00 ,  G11C11/406 ,  H03L7/081

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

公开(公告)号：US10601410B1

公开(公告)日：2020-03-24

申请号：US16179349

申请日：2018-11-02

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: H03K3/017 ,  H03K5/156 ,  H03L7/18 ,  H03K5/19

Abstract: Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.

公开(公告)号：US10594328B2

公开(公告)日：2020-03-17

申请号：US16406480

申请日：2019-05-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/06 ,  H03L7/14 ,  H04L7/04 ,  H03L7/087 ,  H04L5/26 ,  H03L7/18 ,  H03L7/081 ,  H03K5/156

Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.

公开(公告)号：US10560108B2

公开(公告)日：2020-02-11

申请号：US16440818

申请日：2019-06-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/081 ,  H03L7/099 ,  H03L7/10 ,  H03L7/089

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

公开(公告)号：US20200005855A1

公开(公告)日：2020-01-02

申请号：US16557933

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh ,  Tyler J. Gomm

IPC: G11C11/4076 ,  H03K3/017 ,  H03K23/00 ,  H03M7/16 ,  G11C29/02

Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

公开(公告)号：US10516391B2

公开(公告)日：2019-12-24

申请号：US15839531

申请日：2017-12-12

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Kazutaka Miyano

IPC: H03K3/017 ,  H03K5/156 ,  G11C7/22 ,  H03L7/081 ,  G11C7/12 ,  G11C11/4076 ,  G11C7/10

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

公开(公告)号：US10333534B1

公开(公告)日：2019-06-25

申请号：US16150492

申请日：2018-10-03

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: H03L7/08 ,  G06K19/07 ,  G06F1/12 ,  H03L7/00 ,  G06G7/16 ,  G06F1/08 ,  H03K17/00 ,  G05F1/10 ,  H03L7/14 ,  H03L7/087 ,  H03L7/18 ,  H04L5/26 ,  H04L7/04

CPC classification number: H03L7/143 ,  H03K5/1565 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/18 ,  H04L5/26 ,  H04L7/04

Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.

公开(公告)号：US20230412161A1

公开(公告)日：2023-12-21

申请号：US17845764

申请日：2022-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/156 ,  G11C11/4076

CPC classification number: H03K5/1565 ,  G11C11/4076

Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first to fourth clock signals based on an input clock signal, a first duty-cycle detector configured to output a first signal responsive to a comparison between information produced based on the first and second clock signals and based on the third and fourth clock signals, a second duty-cycle detector configured to output a second signal responsive to a comparison between information produced based on the first and fourth clock signals and based on the second and third clock signals, a third duty-cycle detector configured to output a third signal responsive to a comparison between information produced based on the first and third clock signals and based on the second and fourth clock signals, and a duty-cycle adjuster configured to adjust a duty-cycle of the input clock signal responsive to the first to third signals.