中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

32 records (took 0.021 seconds)

    On-die formation of single-crystal semiconductor structures
    22.
    发明授权
    On-die formation of single-crystal semiconductor structures 有权

    公开(公告)号：US11683937B2

    公开(公告)日：2023-06-20

    申请号：US17397725

    申请日：2021-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Jeffery Brandt Hull ,  Anish A. Khandekar ,  Hung-Wei Liu ,  Sameer Chhajed

    IPC: H10B53/20 ,  H01L21/02

    CPC classification number: H10B53/20 ,  H01L21/0257 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02645

    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

    Array Of Capacitors, Array Of Memory Cells, Methods Of Forming An Array Of Capacitors, And Methods Of Forming An Array Of Memory Cells
    23.
    发明申请
    Array Of Capacitors, Array Of Memory Cells, Methods Of Forming An Array Of Capacitors, And Methods Of Forming An Array Of Memory Cells 有权

    公开(公告)号：US20220130845A1

    公开(公告)日：2022-04-28

    申请号：US17567268

    申请日：2022-01-03

    Applicant: Micron Technology, Inc.

    Inventor： Sameer Chhajed ,  Ashonita A. Chavan ,  Mark Fischer ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507 ,  H01L49/02 ,  H01L27/11504 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108

    Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.

    On-die formation of single-crystal semiconductor structures
    24.
    发明授权
    On-die formation of single-crystal semiconductor structures 有权

    公开(公告)号：US12256553B2

    公开(公告)日：2025-03-18

    申请号：US18144708

    申请日：2023-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Jeffery Brandt Hull ,  Anish A. Khandekar ,  Hung-Wei Liu ,  Sameer Chhajed

    IPC: H10B53/20 ,  H01L21/02

    Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

    Array of capacitors, array of memory cells, methods of forming an array of capacitors, and methods of forming an array of memory cells
    28.
    发明授权
    Array of capacitors, array of memory cells, methods of forming an array of capacitors, and methods of forming an array of memory cells 有权

    公开(公告)号：US11244952B2

    公开(公告)日：2022-02-08

    申请号：US16225814

    申请日：2018-12-19

    Applicant: Micron Technology, Inc.

    Inventor： Sameer Chhajed ,  Ashonita A. Chavan ,  Mark Fischer ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507 ,  H01L49/02 ,  H01L27/11504 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108

    Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.

Patent Agency Ranking