-
公开(公告)号：US20200097211A1
公开(公告)日：2020-03-26
申请号：US16138334
申请日：2018-09-21
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, JR. , Kishore Kumar Muchherla , Sampath Ratnam
摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
-
公开(公告)号：US10430116B2
公开(公告)日：2019-10-01
申请号：US15693121
申请日：2017-08-31
发明人： Michael G. Miller , Kishore Kumar Muchherla , Harish Singidi , Sampath Ratnam , Renato C. Padilla, Jr. , Gary F. Besinga , Peter Sean Feeley
摘要： Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
-
公开(公告)号：US20190295660A1
公开(公告)日：2019-09-26
申请号：US16436567
申请日：2019-06-10
发明人： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
-
公开(公告)号：US20190103164A1
公开(公告)日：2019-04-04
申请号：US15571232
申请日：2017-09-30
发明人： Ashutosh Malshe , Harish Singidi , Kishore Kumar Muchherla , Michael G. Miller , Sampath Ratnam , John Zhang , Jie Zhou
摘要： Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
-
公开(公告)号：US11544008B2
公开(公告)日：2023-01-03
申请号：US17232866
申请日：2021-04-16
发明人： Gianni Stephen Alsasua , Karl D. Schuh , Ashutosh Malshe , Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Sampath Ratnam , Harish Reddy Singidi , Renato Padilla, Jr.
IPC分类号： G11C16/04 , G06F3/06 , G06F12/1009 , G11C16/34 , G11C16/26
摘要： A memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
-
公开(公告)号：US11437108B1
公开(公告)日：2022-09-06
申请号：US17230786
申请日：2021-04-14
发明人： Kishore Kumar Muchherla , Karl Schuh , Mustafa N Kaynak , Xiangang Luo , Shane Nowell , Devin Batutis , Sivagnanam Parthasarathy , Sampath Ratnam , Jiangang Wu , Peter Feeley
摘要： A difference between a current temperature and a prior temperature of a memory device is determined. In response to a determination that the difference between the current temperature and the prior temperature of the memory device satisfies a temperature criterion, an amount of voltage shift is measured for a set of memory cells of a block family associated with a first voltage bin of a set of voltage bins at the memory device. The first voltage bin is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the set of memory cells based on the determined amount of voltage shift and a temporary voltage shift offset associated with the difference between the current temperature and the prior temperature for the memory device. In response to a determination that the adjusted amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the set of voltage bins. The second voltage bin is associated with a second voltage offset.
-
公开(公告)号：US20220277787A1
公开(公告)日：2022-09-01
申请号：US17745262
申请日：2022-05-16
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Kishore Kumar Muchherla , Sampath Ratnam , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Renato Padilla, JR.
IPC分类号： G11C11/406 , G06F13/16 , G11C7/04
摘要： Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
-
公开(公告)号：US20210264991A1
公开(公告)日：2021-08-26
申请号：US17318603
申请日：2021-05-12
发明人： Harish Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
-
公开(公告)号：US20210232342A1
公开(公告)日：2021-07-29
申请号：US17232866
申请日：2021-04-16
发明人： Gianni Stephen Alsasua , Karl D. Schuh , Ashutosh Malshe , Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Sampath Ratnam , Harish Reddy Singidi , Renato Padilla, JR.
IPC分类号： G06F3/06 , G06F12/1009 , G11C16/34 , G11C16/26
摘要： Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
-
公开(公告)号：US11031089B2
公开(公告)日：2021-06-08
申请号：US16920154
申请日：2020-07-02
发明人： Harish Reddy Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
-
-
-
-
-
-
-
-
-
搜索结果
73 条记录 (耗时 0.023 秒)