公开(公告)号：US20120126325A1

公开(公告)日：2012-05-24

申请号：US12952376

申请日：2010-11-23

申请人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin

发明人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/823431 ,  H01L21/845

摘要： A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.

摘要翻译： 一种方法包括在半导体衬底的表面上生长多个平行心轴，每个心轴具有至少两个横向相对的侧壁和预定宽度。 该方法还包括在心轴的侧壁上形成第一类型的间隔物，其中两个相邻心轴之间的第一类型的间隔物被间隙分开。 调整预定的心轴宽度以封闭相邻的第一类型间隔件之间的间隙，以形成第二类型的间隔件。 去除心轴以形成第一类型的间隔件的第一类型的翅片，并且在两个相邻的心轴之间从间隔件形成第二类型的翅片。 翅片的第二种类型比第一种翅片宽。

公开(公告)号：US08963257B2

公开(公告)日：2015-02-24

申请号：US13293732

申请日：2011-11-10

申请人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang

发明人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L29/66818 ,  H01L21/2236 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

摘要： The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.

摘要翻译： 本发明涉及Fin场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 在所述基板顶表面上方延伸的第一翅片和第二翅片，其中每个翼片具有顶表面和侧壁; 所述第一和第二翅片之间的绝缘层从所述基板顶表面向上延伸所述翅片; 覆盖第一鳍片的顶表面和第一鳍片的侧壁的第一栅极电介质和覆盖第二鳍片的顶表面和第二鳍片的侧壁的第二栅极电介质具有小于第一厚度的第二厚度; 以及穿过第一栅极电介质和第二栅极电介质两端的导电栅极条。

公开(公告)号：US08633076B2

公开(公告)日：2014-01-21

申请号：US12952376

申请日：2010-11-23

申请人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin

发明人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin

IPC分类号： H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/823431 ,  H01L21/845

摘要： A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.

摘要翻译： 一种方法包括在半导体衬底的表面上生长多个平行心轴，每个心轴具有至少两个横向相对的侧壁和预定宽度。 该方法还包括在心轴的侧壁上形成第一类型的间隔物，其中两个相邻心轴之间的第一类型的间隔物被间隙分开。 调整预定的心轴宽度以封闭相邻的第一类型间隔件之间的间隙，以形成第二类型的间隔件。 去除心轴以形成第一类型的间隔件的第一类型的翅片，并且在两个相邻的心轴之间从间隔件形成第二类型的翅片。 翅片的第二种类型比第一种翅片宽。

公开(公告)号：US08796759B2

公开(公告)日：2014-08-05

申请号：US12837093

申请日：2010-07-15

申请人： Tsu-Hsiu Perng ,  Chih Chieh Yeh ,  Tzu-Chiang Chen ,  Chia-Cheng Ho ,  Chih-Sheng Chang

发明人： Tsu-Hsiu Perng ,  Chih Chieh Yeh ,  Tzu-Chiang Chen ,  Chia-Cheng Ho ,  Chih-Sheng Chang

IPC分类号： H01L29/76

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 示例性的FinFET器件包括半导体衬底; 翅片结构，设置在所述半导体衬底上; 以及设置在鳍结构的一部分上的栅极结构。 栅极结构穿过翅片结构并分离翅片结构的源极区域和漏极区域，源极和漏极区域在其间限定通道。 翅片结构的源极和漏极区域包括应变源极和漏极特征。 应变源特征和应变漏极特征各自包括：具有第一宽度和第一深度的第一部分; 以及设置在所述第一部分下方的第二部分，所述第二部分具有第二宽度和第二深度。 第一宽度大于第二宽度，第一深度小于第二深度。

公开(公告)号：US20120012932A1

公开(公告)日：2012-01-19

申请号：US12837093

申请日：2010-07-15

申请人： Tsu-Hsiu Perng ,  Chih Chieh Yeh ,  Tzu-Chiang Chen ,  Chia-Cheng Ho ,  Chih-Sheng Chang

发明人： Tsu-Hsiu Perng ,  Chih Chieh Yeh ,  Tzu-Chiang Chen ,  Chia-Cheng Ho ,  Chih-Sheng Chang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 示例性的FinFET器件包括半导体衬底; 翅片结构，设置在所述半导体衬底上; 以及设置在鳍结构的一部分上的栅极结构。 栅极结构穿过翅片结构并分离翅片结构的源极区域和漏极区域，源极和漏极区域在其间限定通道。 翅片结构的源极和漏极区域包括应变源极和漏极特征。 应变源特征和应变漏极特征各自包括：具有第一宽度和第一深度的第一部分; 以及设置在所述第一部分下方的第二部分，所述第二部分具有第二宽度和第二深度。 第一宽度大于第二宽度，第一深度小于第二深度。

公开(公告)号：US09245805B2

公开(公告)日：2016-01-26

申请号：US12831903

申请日：2010-07-07

申请人： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

发明人： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC分类号： H01L21/70 ,  H01L27/088 ,  H01L29/78 ,  H01L29/20 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L21/8256 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7848

摘要： An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

摘要翻译： 集成电路结构包括n型鳍式场效应晶体管（FinFET）和p型FinFET。 n型FinFET包括在衬底上的第一锗鳍; 顶表面上的第一栅电介质和第一锗鳍的侧壁; 以及在第一栅极电介质上的第一栅电极。 p型FinFET在衬底上包括第二个锗鳍; 在顶表面上的第二栅电介质和第二锗鳍的侧壁; 和在第二栅极电介质上的第二栅电极。 第一栅电极和第二栅极由具有接近锗的固有能级的功函数的相同材料形成。

公开(公告)号：US08896055B2

公开(公告)日：2014-11-25

申请号：US13585436

申请日：2012-08-14

申请人： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

发明人： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7857

摘要： This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.

摘要翻译： 本说明书涉及在基板上包括基板和翅片结构的鳍状场效应晶体管（FinFET）。 鳍结构包括源极和漏极之间的沟道，其中源极，漏极和沟道具有第一类型掺杂物，并且沟道包括Ge，SiGe或III-V半导体中的至少一个。 FinFET还包括通道上的栅极介电层和栅极电介质层上的栅极。 FinFET还包括邻近栅极的衬底上的氮化物间隔物和氮化物间隔物和栅极之间以及氮化物间隔物和衬底之间的氧化物层。

公开(公告)号：US20090243987A1

公开(公告)日：2009-10-01

申请号：US12383873

申请日：2009-03-30

申请人： Chih-Sheng Chang ,  Chao-Yi Hung ,  Sz-Hsiao Chen ,  Sheng-Tien Cho ,  Chueh-Ju Chen ,  Tsau-Hua Hsieh ,  Chiu-Lien Yang

发明人： Chih-Sheng Chang ,  Chao-Yi Hung ,  Sz-Hsiao Chen ,  Sheng-Tien Cho ,  Chueh-Ju Chen ,  Tsau-Hua Hsieh ,  Chiu-Lien Yang

IPC分类号： G09G3/36

CPC分类号： G09G3/3655 ,  G09G2320/0247 ,  G09G2320/048

摘要： A liquid crystal display (LCD) device includes an LCD panel, and a common voltage generating circuit configured for providing common voltages to the LCD panel. The common voltage generating circuit includes a microprocessor, a timer, a voltage adjustment circuit, and a look up table. The microprocessor is electrically connected to the timer, the look up table, and the voltage adjustment circuit. The timer is configured for recording a continuous operated time of the LCD panel. The look up table is configured for storing optimal common voltages corresponding to each continuous operated time. The microprocessor is configured for reading the optimal common voltage at set intervals corresponding to the continuous operated time, and controlling the voltage adjustment circuit to provide the corresponding optimal common voltage to the LCD panel.

摘要翻译： 液晶显示器（LCD）装置包括LCD面板和配置用于向LCD面板提供公共电压的公共电压产生电路。 公共电压产生电路包括微处理器，定时器，电压调节电路和查找表。 微处理器电连接到定时器，查找表和电压调节电路。 定时器配置为记录LCD面板的连续操作时间。 查找表被配置用于存储对应于每个连续操作时间的最佳公共电压。 微处理器被配置为以对应于连续操作时间的设定间隔读取最佳公共电压，并且控制电压调节电路以向LCD面板提供相应的最佳公共电压。

公开(公告)号：US07268409B2

公开(公告)日：2007-09-11

申请号：US10851021

申请日：2004-05-21

申请人： Bor-Min Tseng ,  Chih-Sheng Chang

发明人： Bor-Min Tseng ,  Chih-Sheng Chang

IPC分类号： H01L27/06

CPC分类号： H01L27/0688 ,  H01F21/00 ,  H01F2017/008 ,  H01L21/8221 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic device including, in one embodiment, a plurality of active devices located at least partially in a substrate, at least one dielectric layer located over the plurality of active devices, and an inductor located over the dielectric layer. At least one of the plurality of active devices is located within a columnar region having a cross-sectional shape substantially conforming to a perimeter of the inductor. The at least one of the plurality of active devices may be biased based on a desired Q factor of the inductor or and/or an operating frequency of the microelectronic device.

摘要翻译： 在一个实施例中，微电子器件包括至少部分地位于衬底中的多个有源器件，位于多个有源器件上方的至少一个电介质层，以及位于电介质层上方的电感器。 多个有源器件中的至少一个位于具有基本上符合电感器的周边的横截面形状的柱状区域内。 多个有源器件中的至少一个可以基于电感器的期望Q因子或/或微电子器件的工作频率而偏置。

公开(公告)号：US07115438B2

公开(公告)日：2006-10-03

申请号：US10834125

申请日：2004-04-29

申请人： Chi-Rong Lin ,  Nien-Chung Jiang ,  Chih-Sheng Chang

发明人： Chi-Rong Lin ,  Nien-Chung Jiang ,  Chih-Sheng Chang

IPC分类号： H01L21/00

CPC分类号： H01L21/76814 ,  H01L21/02063

摘要： A method for manufacturing a complementary metal-oxide semiconductor sensor is provided. The present method provides a semiconductor structure including a plurality of conductors thereon. An inter-metal dielectric layer is formed on the conductors. A silicon nitride film is applied on the inter-metal dielectric layer. An oxide layer is formed on the silicon nitride film. The oxide layer, the silicon nitride film and the inter-metal dielectric are etched to expose portions of the conductors. The oxide layer and the exposed conductors are cleaned in a cleaning step later.

摘要翻译： 提供一种制造互补金属氧化物半导体传感器的方法。 本方法提供了包括多个导体的半导体结构。 在导体上形成金属间介电层。 在金属间电介质层上施加氮化硅膜。 在氮化硅膜上形成氧化物层。 蚀刻氧化物层，氮化硅膜和金属间电介质以暴露部分导体。 氧化物层和暴露的导体在稍后的清洁步骤中被清洁。