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1.发明授权Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications 有权使用等离子体掺杂和蚀刻的三维晶体管应用的选择性鳍形成工艺公开(公告)号：US08946829B2
公开(公告)日：2015-02-03
申请号：US13273527
申请日：2011-10-14
申请人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yi-Tang Lin , Chih-Sheng Chang , Chi-Wen Liu
发明人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yi-Tang Lin , Chih-Sheng Chang , Chi-Wen Liu
IPC分类号： H01L27/088 , H01L21/8238 , H01L21/84 , H01L29/78 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/66
CPC分类号： H01L21/823431 , H01L21/265 , H01L21/31111 , H01L21/76224 , H01L21/823481 , H01L21/823821 , H01L21/845 , H01L27/088 , H01L27/0924 , H01L27/1211 , H01L29/06 , H01L29/66818 , H01L29/78 , H01L29/7853 , H01L29/7854
摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.
摘要翻译： 半导体装置包括具有成形翅片和规则翅片的鳍状场效应晶体管（FinFET）。 成形翅片的顶部可以比普通翅片的顶部更小，更大，更薄或更短。 成形翅片和规则翅片的底部是相同的。 FinFET可以仅具有一个或多个成形翅片，一个或多个规则翅片，或者成形翅片和规则翅片的混合物。 形成一个鳍片的半导体制造工艺包括形成一个鳍片的光刻开口，可选地掺杂鳍片的一部分，以及蚀刻鳍片的一部分。
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公开(公告)号：US08963257B2
公开(公告)日：2015-02-24
申请号：US13293732
申请日：2011-11-10
IPC分类号： H01L27/088 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/66
CPC分类号： H01L29/66818 , H01L21/2236 , H01L21/823431 , H01L21/823462 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823857 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.
摘要翻译： 本发明涉及Fin场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 在所述基板顶表面上方延伸的第一翅片和第二翅片，其中每个翼片具有顶表面和侧壁; 所述第一和第二翅片之间的绝缘层从所述基板顶表面向上延伸所述翅片; 覆盖第一鳍片的顶表面和第一鳍片的侧壁的第一栅极电介质和覆盖第二鳍片的顶表面和第二鳍片的侧壁的第二栅极电介质具有小于第一厚度的第二厚度; 以及穿过第一栅极电介质和第二栅极电介质两端的导电栅极条。
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3.发明申请FIN FIELD-EFFECT TRANSISTORS HAVING CONTROLLED FIN HEIGHT AND METHOD OF MAKING 有权具有控制熔融高度的FIN场效应晶体管和制造方法公开(公告)号：US20130221491A1
公开(公告)日：2013-08-29
申请号：US13403630
申请日：2012-02-23
申请人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yuan-Fu Shao , Wen-Huei Guo , Tung Ying Lee
发明人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yuan-Fu Shao , Wen-Huei Guo , Tung Ying Lee
IPC分类号： H01L29/02 , H01L21/336
CPC分类号： H01L29/42368 , H01L21/823431 , H01L21/845 , H01L29/02 , H01L29/06 , H01L29/0653 , H01L29/7856
摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.
摘要翻译： 半导体装置包括具有受控制的翅片高度的鳍状场效应晶体管（FinFET）。 该装置包括高翅片密度区域和低翅片密度区域。 每个翅片密度区域包括翅片和翅片之间的电介质材料。 电介质材料包括用于不同翅片密度区域的不同掺杂剂浓度，并且是与沉积物相同的材料。
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4.发明授权Method of forming fin field-effect transistors having controlled fin height 有权形成具有受控翅片高度的鳍状场效应晶体管的方法公开(公告)号：US09041158B2
公开(公告)日：2015-05-26
申请号：US13403630
申请日：2012-02-23
申请人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yuan-Fu Shao , Wen-Huei Guo , Tung Ying Lee
发明人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yuan-Fu Shao , Wen-Huei Guo , Tung Ying Lee
CPC分类号： H01L29/42368 , H01L21/823431 , H01L21/845 , H01L29/02 , H01L29/06 , H01L29/0653 , H01L29/7856
摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.
摘要翻译： 半导体装置包括具有受控制的翅片高度的鳍状场效应晶体管（FinFET）。 该装置包括高翅片密度区域和低翅片密度区域。 每个翅片密度区域包括翅片和翅片之间的电介质材料。 电介质材料包括用于不同翅片密度区域的不同掺杂剂浓度，并且是与沉积物相同的材料。
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公开(公告)号：US20140042500A1
公开(公告)日：2014-02-13
申请号：US13571201
申请日：2012-08-09
IPC分类号： H01L23/48 , H01L21/20 , H01L29/772
CPC分类号： H01L29/7851 , H01L21/28525 , H01L21/28568 , H01L21/324 , H01L21/76224 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L27/0886 , H01L29/165 , H01L29/41791 , H01L29/45 , H01L29/49 , H01L29/495 , H01L29/4958 , H01L29/518 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.
摘要翻译： 本公开涉及一种半导体器件。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的空腔; 空腔中的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在应变材料上的含Ge介电层; 以及在含Ge介电层上的金属层。
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公开(公告)号：US09136383B2
公开(公告)日：2015-09-15
申请号：US13571201
申请日：2012-08-09
IPC分类号： H01L29/49 , H01L29/40 , H01L29/78 , H01L21/8234 , H01L29/51 , H01L21/8238 , H01L29/417 , H01L21/285 , H01L21/762 , H01L29/165
CPC分类号： H01L29/7851 , H01L21/28525 , H01L21/28568 , H01L21/324 , H01L21/76224 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L27/0886 , H01L29/165 , H01L29/41791 , H01L29/45 , H01L29/49 , H01L29/495 , H01L29/4958 , H01L29/518 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.
摘要翻译： 本公开涉及一种半导体器件。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的空腔; 空腔中的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在应变材料上的含Ge介电层; 以及在含Ge介电层上的金属层。
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公开(公告)号：US08816444B2
公开(公告)日：2014-08-26
申请号：US13416862
申请日：2012-03-09
申请人： Clement Hsingjen Wann , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh , Ting-Chu Ko , Chung-Hsien Chen
发明人： Clement Hsingjen Wann , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh , Ting-Chu Ko , Chung-Hsien Chen
IPC分类号： H01L27/088
CPC分类号： H01L27/0886 , G03F1/00 , G06F17/5068 , G06F17/5081 , H01L21/823821 , H01L21/845 , H01L23/48 , H01L27/0207 , H01L29/41791 , H01L29/66795 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
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公开(公告)号：US08621406B2
公开(公告)日：2013-12-31
申请号：US13416642
申请日：2012-03-09
申请人： Cheok-Kei Lei , Yi-Tang Lin , Hsiao-Hui Chen , Yu-Ning Chang , Shu-Yu Chen , Chien-Wen Chen , Chih-Sheng Chang , Clement Hsingjen Wann
发明人： Cheok-Kei Lei , Yi-Tang Lin , Hsiao-Hui Chen , Yu-Ning Chang , Shu-Yu Chen , Chien-Wen Chen , Chih-Sheng Chang , Clement Hsingjen Wann
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/823821
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.
摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局并生成相应的FinFET结构。
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公开(公告)号：US08799833B2
公开(公告)日：2014-08-05
申请号：US13416907
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
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公开(公告)号：US08726220B2
公开(公告)日：2014-05-13
申请号：US13416742
申请日：2012-03-09
申请人： Yi-Tang Lin , Cheok-Kei Lei , Shu-Yu Chen , Yu-Ning Chang , Hsiao-Hui Chen , Chih-Sheng Chang , Chien-Wen Chen , Clement Hsingjen Wann
发明人： Yi-Tang Lin , Cheok-Kei Lei , Shu-Yu Chen , Yu-Ning Chang , Hsiao-Hui Chen , Chih-Sheng Chang , Chien-Wen Chen , Clement Hsingjen Wann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , H01L21/823821 , H01L27/0207
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局，并以相符的方式生成对应的FinFET结构。 然后优化所得的FinFET结构。 在验证并输出FinFET布局之前，可能会产生虚拟图案和新的金属层。
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