公开(公告)号：US06420752B1

公开(公告)日：2002-07-16

申请号：US09502163

申请日：2000-02-11

申请人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

发明人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/115 ,  H01L2924/3011

摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

摘要翻译： 公开了一种用于最小化自动掺杂问题的半导体器件。 蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。 衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷 电介质层自动掺入源和漏极。

公开(公告)号：US07341956B1

公开(公告)日：2008-03-11

申请号：US11100563

申请日：2005-04-07

申请人： Hirokazu Tokuno ,  Minh-Van Ngo ,  Angela T. Hui ,  Cinti Xiaohua Chen

发明人： Hirokazu Tokuno ,  Minh-Van Ngo ,  Angela T. Hui ,  Cinti Xiaohua Chen

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L27/11568 ,  H01L21/266

摘要： A method includes forming a group of disposable hard mask structures on a semiconductor device that includes a group of memory cells. The method further includes using the disposable hard mask structures to precisely control a junction profile of the memory cells.

摘要翻译： 一种方法包括在包括一组存储器单元的半导体器件上形成一组一次性硬掩模结构。 该方法还包括使用一次性硬掩模结构来精确控制存储器单元的接合轮廓。

公开(公告)号：US06836398B1

公开(公告)日：2004-12-28

申请号：US10284769

申请日：2002-10-31

申请人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Minh Van Ngo ,  Mark S. Chang ,  Sergey D. Lopatin ,  Angela T. Hui ,  Christopher F. Lyons ,  Patrick K. Cheung ,  Ashok M. Khathuria

发明人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Minh Van Ngo ,  Mark S. Chang ,  Sergey D. Lopatin ,  Angela T. Hui ,  Christopher F. Lyons ,  Patrick K. Cheung ,  Ashok M. Khathuria

IPC分类号： H01G435

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L21/3212 ,  H01L27/285 ,  H01L28/75

摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.

摘要翻译： 本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。 本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。 在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。 还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。 因此，钝化层与用于形成电极的还原CMP工艺结合形成。

公开(公告)号：US06479348B1

公开(公告)日：2002-11-12

申请号：US10109516

申请日：2002-08-27

申请人： Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Angela T. Hui

发明人： Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Angela T. Hui

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.

摘要翻译： 提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。 在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。 字线材料和硬掩模材料沉积在字线材料上。 光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。 使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。 然后去除图案化的光致抗蚀剂。 硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。 使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

公开(公告)号：US06291296B1

公开(公告)日：2001-09-18

申请号：US09416382

申请日：1999-10-12

申请人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

发明人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/951

摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.

摘要翻译： 本发明提供了一种从基板表面上的电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。 在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层，而不会在电介质层，形成在衬底上的源极/漏极区域的划伤和/或降解，以及形成在顶部的硅化物层 堆叠门结构。 CH3F / O2蚀刻化学以比介电层，源/漏区和硅化物层的蚀刻速率明显更快的速率蚀刻ARC层。 此外，通过在形成钨触点之前，通过用钨填充形成在电介质层中的接触开口来去除ARC层，消除了由于ARC层去除引起的钨触点的潜在划痕。

公开(公告)号：US6137126A

公开(公告)日：2000-10-24

申请号：US375499

申请日：1999-08-17

申请人： Steven C. Avanzino ,  Minh Van Ngo ,  Angela T. Hui ,  Chun Jiang ,  Hamid Partovi

发明人： Steven C. Avanzino ,  Minh Van Ngo ,  Angela T. Hui ,  Chun Jiang ,  Hamid Partovi

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/49 ,  H01L29/72 ,  H01L27/10

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/4983 ,  Y10S257/90

摘要： The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.

摘要翻译： 当形成具有浅延伸的源极/漏极区域时，通过在栅电极的侧表面上使用SiC侧壁间隔来减小晶体管的栅电极和局部互连之间的电容。 实施例包括将SiC侧壁间隔物形成为具有小于约3.2的介电常数的约500安培的宽度至约800安培角，沉积氧化硅介电层，以及通过介电层形成局部互连。 栅电极和局部互连之间的所得复合介电常数为约4.2至约4.7。

公开(公告)号：US07572727B1

公开(公告)日：2009-08-11

申请号：US10934828

申请日：2004-09-02

申请人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

发明人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

摘要翻译： 本发明是一种半导体接触形成系统和方法。 接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。 该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。 通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。 导电材料（例如，钨）沉积在接触区域中。

公开(公告)号：US07977797B2

公开(公告)日：2011-07-12

申请号：US12539480

申请日：2009-08-11

申请人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

发明人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

IPC分类号： H01L23/522

CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

摘要翻译： 本发明是一种半导体接触形成系统和方法。 接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。 该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。 通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。 导电材料（例如，钨）沉积在接触区域中。

公开(公告)号：US07361587B1

公开(公告)日：2008-04-22

申请号：US10934923

申请日：2004-09-02

申请人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

发明人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  Y10S438/97

摘要： The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region width are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

摘要翻译： 本发明是形成接触绝缘区域的半导体接触形成系统和方法，该接触绝缘区域包括有助于形成接触的多个蚀刻停止子层。 该契约形成过程提供相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，多次蚀刻停止触点形成工艺，其中沉积包括多个蚀刻停止层的多重蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除靠近金属层，并且较小的部分被移除到靠近基板的位置。 不同的接触区域宽度通过执行由多个蚀刻停止绝缘层中的多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现。 导电材料（例如，钨）沉积在接触区域中。

公开(公告)号：US07015135B2

公开(公告)日：2006-03-21

申请号：US10316569

申请日：2002-12-10

申请人： Angela T. Hui ,  Wenmei Li ,  Amy C. Tu

发明人： Angela T. Hui ,  Wenmei Li ,  Amy C. Tu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802

摘要： A method and system for providing at least one contact in a semiconductor device. The semiconductor device includes a substrate, an etch stop layer, an interlayer dielectric on the etch stop layer, an anti-reflective coating layer on the interlayer dielectric, and at least one feature below the etch stop layer. A resist mask having an aperture and residing on the anti-reflective coating layer is provided. The aperture is above an exposed portion of the anti-reflective coating layer. The method and system include etching the exposed anti-reflective coating layer and the underlying interlayer dielectric without etching through the etch stop layer, thereby providing a portion of at least one contact hole. The method and system also include removing the resist mask in situ, removing a portion of the etch stop layer exposed in the portion of the contact hole, and filling the contact hole with a conductive material.

摘要翻译： 一种用于在半导体器件中提供至少一个触点的方法和系统。 半导体器件包括衬底，蚀刻停止层，蚀刻停止层上的层间电介质，层间电介质上的抗反射涂层，以及蚀刻停止层下方的至少一个特征。 提供具有孔径并且位于抗反射涂层上的抗蚀剂掩模。 孔径在抗反射涂层的暴露部分之上。 该方法和系统包括蚀刻暴露的抗反射涂层和下层层间电介质，而不通过蚀刻停止层进行蚀刻，由此提供至少一个接触孔的一部分。 该方法和系统还包括在原位去除抗蚀剂掩模，去除暴露在接触孔部分中的一部分蚀刻停止层，并用导电材料填充该接触孔。