公开(公告)号：US08492867B2

公开(公告)日：2013-07-23

申请号：US13164246

申请日：2011-06-20

申请人： Kensaku Yamamoto ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8613

摘要： A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

摘要翻译： 半导体器件包括半导体衬底和电场端子部分。 半导体衬底包括衬底，设置在衬底的表面上的漂移层和设置在漂移层的表面上的基底层。 半导体衬底被分成其中设置半导体元件的单元区域和围绕单元区域的外围区域。 基底区域具有位于整个电池区域和外围区域的同一平面上的底面，并且提供位于周边区域中的电场弛豫层。 电场端子部围绕电池区域和电场缓和层的一部分，从电场缓和层的表面向漂移层贯通电场缓和层。

公开(公告)号：US08436365B2

公开(公告)日：2013-05-07

申请号：US13031280

申请日：2011-02-21

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/16 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L29/47 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/872

摘要： A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.

摘要翻译： 具有肖特基势垒二极管的SiC半导体器件包括：由SiC制成并具有第一导电类型的衬底，其中所述衬底包括主表面和后表面; 由SiC制成并具有第一导电类型的漂移层，其中所述漂移层设置在所述衬底的主表面上并且具有低于所述衬底的杂质浓度; 肖特基电极，设置在漂移层上并与漂移层的表面具有肖特基接触; 以及设置在基板的后表面上的欧姆电极。 肖特基电极以使得肖特基电极的晶格与漂移层的晶格匹配的方式直接接触漂移层。

公开(公告)号：US08163637B2

公开(公告)日：2012-04-24

申请号：US12975832

申请日：2010-12-22

申请人： Masaki Konishi ,  Hirokazu Fujiwara ,  Takeshi Endo ,  Takeo Yamamoto ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Masaki Konishi ,  Hirokazu Fujiwara ,  Takeshi Endo ,  Takeo Yamamoto ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L21/425

CPC分类号： H01L21/0465 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor region, of the second layer may be removed. Next, second conductive type ion impurities may be injected from upper sides of the first and second layers to the semiconductor layer after the removing step.

摘要翻译： 首先，可以在半导体层的上表面上形成由Ni构成的第一层或包含Ni的合金。 接下来，可以在第一层的上表面上形成由氧化硅制成的第二层。 接下来，可以去除对应于第二层的半导体区域的部分。 接下来，可以在去除步骤之后，将第二导电型离子杂质从第一层和第二层的上侧注入半导体层。

公开(公告)号：US20110204383A1

公开(公告)日：2011-08-25

申请号：US13031280

申请日：2011-02-21

申请人： Takeo YAMAMOTO ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

发明人： Takeo YAMAMOTO ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/24 ,  H01L21/329 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/47 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/872

摘要： A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.

摘要翻译： 具有肖特基势垒二极管的SiC半导体器件包括：由SiC制成并具有第一导电类型的衬底，其中所述衬底包括主表面和后表面; 由SiC制成并具有第一导电类型的漂移层，其中所述漂移层设置在所述衬底的主表面上并且具有低于所述衬底的杂质浓度; 肖特基电极，设置在漂移层上并与漂移层的表面具有肖特基接触; 以及设置在基板的后表面上的欧姆电极。 肖特基电极以使得肖特基电极的晶格与漂移层的晶格匹配的方式直接接触漂移层。

公开(公告)号：US20100244049A1

公开(公告)日：2010-09-30

申请号：US12659853

申请日：2010-03-23

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L29/47 ,  H01L29/24 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0465 ,  H01L21/0495 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/872

摘要： A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.

摘要翻译： 具有肖特基势垒二极管的碳化硅半导体器件包括第一导电型碳化硅衬底，在衬底的第一表面上的第一导电型碳化硅漂移层，与漂移层形成肖特基接触的肖特基电极和欧姆 电极在基板的第二表面上。 肖特基电极包括与漂移层直接接触的氧化物层。 氧化物层由钼，钛，镍或这些元素中的至少两种的合金的氧化物制成。

公开(公告)号：US20090230405A1

公开(公告)日：2009-09-17

申请号：US12382369

申请日：2009-03-13

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact.

摘要翻译： 二极管的制造方法包括：在晶体生长方法的N型半导体层上形成P型半导体膜; 在P型半导体膜上形成第一金属膜，使得第一金属膜与欧姆接触的P型半导体膜接触; 在所述第一金属膜上形成具有开口的掩模; 经由所述开口蚀刻所述第一金属膜的一部分和所述P型半导体膜的一部分，使得所述N型半导体层的一部分露出; 并且在N型半导体层的一部分上形成第二金属膜，使得第二金属膜以肖特基接触接触N型半导体层。

公开(公告)号：US5304822A

公开(公告)日：1994-04-19

申请号：US877700

申请日：1992-05-01

申请人： Haruo Takagi ,  Shinobu Aoki ,  Yukihiko Watanabe ,  Hiroshi Tadano

发明人： Haruo Takagi ,  Shinobu Aoki ,  Yukihiko Watanabe ,  Hiroshi Tadano

IPC分类号： H01L29/417 ,  H01L29/772 ,  H01L29/80 ,  H01L29/74

CPC分类号： H01L29/41741 ,  H01L29/7722

摘要： A static induction type semiconductor device of a surface gate type, includes a source region, gate region and drain region. A channel region is formed between the drain region and the source region, such that when a bias potential is applied between the gate region and the source region, carriers flow to the drain region from the source region via the channel region. A source electrode is provided on the semiconductor layer. A source contact region is provided between the source electrode and the source region to establish electrical connection therebetween. The source contact region is segmented into a plurality of smaller regions or sections whose total area is smaller than the area of the corresponding portion of the source region, for improving the current gain, and for preventing or significantly reducing local current concentration.

摘要翻译： 表面栅型静电感应型半导体器件包括源极区，栅极区和漏极区。 在漏极区域和源极区域之间形成沟道区域，使得当在栅极区域和源极区域之间施加偏置电位时，载流子经由沟道区域从源极区域流到漏极区域。 源电极设置在半导体层上。 源极接触区域设置在源电极和源极区域之间以在它们之间建立电连接。 源极接触区域被分割为总面积小于源极区域的相应部分的面积的多个较小区域或部分，用于改善电流增益，以及用于防止或显着降低局部电流集中。

公开(公告)号：US09640651B2

公开(公告)日：2017-05-02

申请号：US15116288

申请日：2014-10-06

申请人： Hidefumi Takaya ,  Jun Saito ,  Akitaka Soeno ,  Kimimori Hamada ,  Shoji Mizuno ,  Sachiko Aoi ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Jun Saito ,  Akitaka Soeno ,  Kimimori Hamada ,  Shoji Mizuno ,  Sachiko Aoi ,  Yukihiko Watanabe

IPC分类号： H01L29/94 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L29/16

CPC分类号： H01L29/7811 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

公开(公告)号：US08748975B2

公开(公告)日：2014-06-10

申请号：US13712343

申请日：2012-12-12

申请人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

发明人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/26506 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

摘要： A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.

摘要翻译： 提供了具有半导体衬底的开关元件。 沟槽栅电极形成在半导体衬底的上表面中。 在与半导体衬底中的栅极绝缘膜接触的区域中形成n型第一半导体区域，p型第二半导体区域和n型第三半导体区域。 在第二半导体区域下方的位置处，形成连接到第二半导体区域的p型第四半导体区域，并且经由第三半导体区域与栅极绝缘膜相对并且含有硼。 在第三半导体区域的至少一部分中，形成具有比在半导体衬底的下表面露出的半导体区域更高的碳浓度的高浓度含碳区域，位于第四半导体区域 以及与第四半导体区域接触的栅极绝缘膜。

公开(公告)号：US20130330896A1

公开(公告)日：2013-12-12

申请号：US14000901

申请日：2012-09-04

申请人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/3065 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

摘要： A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening.

摘要翻译： 碳化硅半导体器件的制造方法包括：在碳化硅衬底上形成漂移层; 在漂移层的表面部分上或其中形成基底层; 在所述基底层的表面部分中形成源区; 形成沟槽以穿透基层并到达漂移层; 在沟槽中的栅极绝缘膜上形成栅电极; 形成与源极区域和基极层电连接的源电极; 以及在所述基板的背面上形成漏电极。 沟槽的形成包括：使基底表面变平; 并进行蚀刻以在平坦化之后形成沟槽。