公开(公告)号：US20250095922A1

公开(公告)日：2025-03-20

申请号：US18966314

申请日：2024-12-03

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

公开(公告)号：US20220102078A1

公开(公告)日：2022-03-31

申请号：US17487353

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a multilayer body including an inner layer portion including dielectric layers and internal electrode layers alternately laminated therein, two outer layer portions respectively provided on both sides of the inner layer portion in a lamination direction, and two side gap portions respectively provided on both side surfaces of the inner layer portion and the outer layer portions, in a width direction intersecting the lamination direction, and external electrodes respectively provided on both end surfaces of the multilayer body in a length direction intersecting the lamination direction and the width direction, and each connected to the internal electrode layers, wherein nickel and magnesium are segregated between the side gap portions and the outer layer portions.

公开(公告)号：US20220102075A1

公开(公告)日：2022-03-31

申请号：US17487346

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, base electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers and each including glass and copper, and plated layers respectively provided on an outer side of the base electrode layers. A protective layer including sulfur is provided between the glass included in the base electrode layers and the plated layers.

公开(公告)号：US20210202181A1

公开(公告)日：2021-07-01

申请号：US17131899

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro WAKASHIMA ,  Yuta SAITO ,  Yuta KUROSU ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008

Abstract: In a multilayer ceramic capacitor includes, in a plane including a center portion in a length direction, and a stacking direction and a width direction of a first dielectric ceramic layer, where a thickness at a center portion in the stacking direction is T1, a thickness at an end of the first dielectric ceramic layer in the width direction is T2, and respective thicknesses between an end of a first internal electrode layer in the length direction not connected to a second external electrode, and the second external electrode, and between an end of the second internal electrode layer in the length direction not connected to the first external electrode, and the first external electrode is T3, a difference in thickness between T1 and T2 is within about 10% of T1, and a thickness of T3 is greater than T1 and T2 and a difference thereof is about 10% or more of T1 and T2.

公开(公告)号：US20210202180A1

公开(公告)日：2021-07-01

申请号：US17131898

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki FUKUNAGA ,  Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/12 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a third segregation by each of metal elements of a first segregation and a second segregation is provided at each of a first corner region in which an end in a length direction in which the first segregation is provided overlaps an end in a width direction in which the second segregation is provided in a first internal electrode layer, and a second corner region in which an end in the length direction in which the second segregation is provided overlaps an end in the width direction in which the second segregation is provided in a second internal electrode layer.

公开(公告)号：US20180040428A1

公开(公告)日：2018-02-08

申请号：US15669038

申请日：2017-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro WAKASHIMA ,  Yuta SAITO ,  Kohei SHIMADA ,  Naobumi IKEGAMI

IPC: H01G4/38 ,  H01G4/248 ,  H05K1/18 ,  H01G4/30 ,  H01G4/012

CPC classification number: H01G4/38 ,  H01G2/06 ,  H01G4/012 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01G4/308 ,  H05K1/0295 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10522

Abstract: A mounting substrate on which at least any one of three kinds of electronic components including a first electronic component, a second electronic component, and a third electronic component are able to be mounted includes a pair of first edge portions and a pair of second edge portions. When a dimension of the first electronic component in its length direction is designated as L1, a dimension of the first electronic component in its width direction is designated as W1, a dimension of the second electronic component in its length direction is designated as L2, and a dimension of the second electronic component in its width direction is designated as W2, a dimension of the third electronic component in its width direction is any one of W1 and W2, and a dimension of the third electronic component in its length direction is L2 when the dimension of the third electronic component in its width direction is W1, and is L1 when the dimension of the third electronic component in its width direction is W2. At least one or more of the third electronic components are mounted on the mounting substrate.