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公开(公告)号：US09484815B2
公开(公告)日：2016-11-01
申请号：US14055819
申请日：2013-10-16
Applicant: NVIDIA Corporation
Inventor： William J. Dally
CPC classification number: H02M3/158 , H02M3/156 , H02M2003/1566
Abstract: A system and method are provided for controlling a switching voltage regulator circuit. An energy difference between a stored energy of a switching voltage regulator and a target energy is determined. A control variable of the switching voltage regulator is computed based on the energy difference and the control variable is applied to a current control mechanism of the switching voltage regulator. In one embodiment, the control variable is pulse width of a control signal.
Abstract translation: 提供了用于控制开关电压调节器电路的系统和方法。 确定开关电压调节器的存储能量与目标能量之间的能量差。 基于能量差计算开关电压调节器的控制变量，并且将控制变量应用于开关电压调节器的电流控制机构。 在一个实施例中，控制变量是控制信号的脉冲宽度。
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22.发明授权System, method, and computer program product for executing casting-arithmetic instructions 有权用于执行铸造算术指令的系统，方法和计算机程序产品公开(公告)号：US09477477B2
公开(公告)日：2016-10-25
申请号：US14161628
申请日：2014-01-22
Applicant: NVIDIA Corporation
Inventor： William J. Dally
CPC classification number: G06F9/30185 , G06F8/437 , G06F8/447 , G06F9/3001 , G06F9/30025
Abstract: A system, method, and computer program product are provided for executing casting-arithmetic instructions. The method comprises receiving a casting-arithmetic instruction that specifies an arithmetic operation to be performed on input data and at least one casting operation of an input casting operation and an output casting operation. Upon determining that the casting-arithmetic instruction specifies the input casting operation, the input casting operation is performed on identified terms comprising the input data. Then the arithmetic operation is performed on the input data to generate an arithmetic result. Upon determining that the casting-arithmetic instruction specifies the output casting operation, the output casting operation is performed on the arithmetic result.
Abstract translation: 提供了一种用于执行铸造算术指令的系统，方法和计算机程序产品。 该方法包括接收指定对输入数据执行的算术运算和输入转换操作和输出转换操作的至少一个投射操作的铸造算术指令。 在确定铸造算术指令指定输入铸造操作时，对包括输入数据的识别项执行输入铸造操作。 然后对输入数据进行算术运算，生成运算结果。 在确定铸造算术指令指定输出转换操作时，对算术结果执行输出转换操作。
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23.发明授权Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled 有权周期性同步器使用缩短的时序余量来生成被验证或召回的推测同步输出信号公开(公告)号：US09471091B2
公开(公告)日：2016-10-18
申请号：US13688170
申请日：2012-11-28
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Stephen G. Tell
CPC classification number: G06F1/12
Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.
Abstract translation: 提供了一种用于推测周期性同步的方法和系统。 接收表示相对于在至少一个周期测量的第一时钟信号的第二时钟信号的测量相位的相位值。 还接收表示相对于先前测量的至少一个周期的第一时钟信号的第二时钟信号的周期的周期值。 基于相位值和周期值确定缩短的定时裕度。 基于减小的时序余量产生推测同步的输出信号。
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公开(公告)号：US20160043569A1
公开(公告)日：2016-02-11
申请号：US14815853
申请日：2015-07-31
Applicant: NVIDIA Corporation
CPC classification number: H01F27/027 , H01F27/24 , H01F27/2823 , H01F38/14 , H02J5/00 , H02J5/005 , H02J50/10
Abstract: A magnetic power supply coupling system is disclosed. An integrated circuit module includes an integrated circuit die and a secondary winding that is configured to generate an induced, alternating current based on a magnetic flux. A primary winding is external to the integrated circuit module, proximate to the integrated circuit module, and coupled to a main power supply corresponding to an alternating current that generates the magnetic flux. The induced, alternating current is converted into a direct current at a voltage level to supply power to the integrated circuit die.
Abstract translation: 公开了一种磁电源耦合系统。 集成电路模块包括集成电路管芯和次级绕组，其被配置为基于磁通量产生感应的交流电流。 初级绕组在集成电路模块的外部，靠近集成电路模块，并且耦合到对应于产生磁通量的交流电的主电源。 感应的交流电被转换成电压电平的直流电，以向集成电路管芯供电。
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公开(公告)号：US09251870B2
公开(公告)日：2016-02-02
申请号：US13857099
申请日：2013-04-04
Applicant: NVIDIA Corporation
Inventor： William J. Dally , John W. Poulton , Thomas Hastings Greer, III , Brucek Kurdo Khailany , Carl Thomas Gray
IPC: G11C11/40 , G11C7/00 , G11C11/41 , G11C7/10 , G11C11/4096
CPC classification number: G11C7/00 , G11C7/1057 , G11C7/1069 , G11C11/4096 , G11C11/41 , H01L2224/0401 , H01L2224/16145 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.
Abstract translation: 提供用于发送信号的系统。 该系统包括第一处理单元，高速缓冲存储器和封装。 第一处理单元包括第一接地参考单端信令（GRS）接口电路，第二处理单元包括第二GRS接口电路。 高速缓冲存储器包括第三和第四GRS接口电路。 该包装包括将第一GRS接口耦合到第三GRS接口并将第二GRS接口耦合到第四GRS接口的一个或多个电迹线，其中第一GRS接口电路，第二GRS接口，第三GRS接口和 第四GRS接口电路各自被配置为通过在一个迹线和地面网络之间放电电容器来沿着一个或多个电迹线的一个迹线发送脉冲。
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Patent Agency Ranking
公开(公告)号：US09164134B2
公开(公告)日：2015-10-20
申请号：US13676021
申请日：2012-11-13
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Stephen G. Tell
CPC classification number: G01R25/00
Abstract: A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples.
Abstract translation: 提供了一种用于时钟相位检测的方法和系统。 产生一组第一时钟信号的延迟版本。 第一时钟的延迟版本集用于采样第二时钟信号，产生与第一时钟信号相对应的域中的采样序列。 至少一个边缘指示位于样本序列内。
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公开(公告)号：US09071244B2
公开(公告)日：2015-06-30
申请号：US14055823
申请日：2013-10-16
Applicant: NVIDIA Corporation
Inventor： John W. Poulton , Thomas Hastings Greer, III , William J. Dally
CPC classification number: H03K17/16 , H04B1/04 , H04L25/0274 , H04L25/028 , H04L25/0292 , H04L25/03878
Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.
Abstract translation: 本发明的一个实施例提出了用于发送和接收地参考单端信号的机制。 发射机将直流（DC）到DC转换器组合，其中包括具有2：1时钟多路复用器的飞跨电容器，以驱动单端信号线。 发射机驱动一对对地面电源电平对称的电压。 信号电流返回到接地平面，以最小化作为不同信号线之间的串扰源的噪声的产生。 通过电源引入的噪声与数据的切换速率相关，并且可以使用均衡器电路来减小。
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公开(公告)号：US20150015314A1
公开(公告)日：2015-01-15
申请号：US13942614
申请日：2013-07-15
Applicant: NVIDIA Corporation
Inventor： William J. Dally
IPC: H03L7/00
CPC classification number: H03L7/00 , H04L7/0012 , H04L7/0037 , H04L7/0041
Abstract: A method and a system are provided for synchronizing a signal. A keep out window is defined relative to a second clock signal and an edge detection signal is generated that indicates if an edge of a first clock signal is within the keep out window. The edge detection signal may be filtered. An input signal is received in a domain corresponding to the first clock signal and a delayed input signal is generated. Based on the edge detection signal or the filtered edge detection signal, either the input signal or the delayed input signal is selected, to produce an output signal in a domain corresponding to the second clock signal.
Abstract translation: 提供了一种用于使信号同步的方法和系统。 相对于第二时钟信号定义保持窗口，并且生成指示第一时钟信号的边缘在保持输出窗口内的边缘检测信号。 可以对边缘检测信号进行滤波。 在对应于第一时钟信号的域中接收输入信号，并且产生延迟的输入信号。 基于边缘检测信号或滤波边沿检测信号，选择输入信号或延迟输入信号，以产生与第二时钟信号对应的域中的输出信号。
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公开(公告)号：US20140317361A1
公开(公告)日：2014-10-23
申请号：US13865136
申请日：2013-04-17
Applicant: NVIDIA CORPORATION
Inventor： William J. Dally
IPC: G06F12/00
CPC classification number: G06F13/161
Abstract: A method and a system are provided for controlling memory accesses. Memory access requests including at least a first speculative memory access request and a first non-speculative memory access request are received and a memory access request is selected from the memory access requests. A memory access command is generated to process the selected memory access request.
Abstract translation: 提供了一种用于控制存储器访问的方法和系统。 接收包括至少第一推测存储器访问请求和第一非推测存储器访问请求的存储器访问请求，并且从存储器访问请求中选择存储器访问请求。 生成存储器访问命令以处理所选择的存储器访问请求。
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公开(公告)号：US20140312860A1
公开(公告)日：2014-10-23
申请号：US13868969
申请日：2013-04-23
Applicant: NVIDIA CORPORATION
Inventor： William J. Dally
CPC classification number: H02M3/1588 , H02M3/1584 , Y02B70/1466
Abstract: A system and method are provided for controlling a soft-switched modified buck regulator circuit. A voltage (Vx) across or a current through a pull-down switching mechanism within the modified buck regulator circuit is sensed when the pull-down switching mechanism is enabled, where the pull-down switching mechanism is coupled to an upstream end of an inductor and is coupled in parallel with a capacitor. A target time when the pull-down switching mechanism will be disabled (tlf) is computed and the pull-down transistor is disabled at the computed target time.
Abstract translation: 提供了一种用于控制软开关改进的降压调节器电路的系统和方法。 当下拉开关机构启用时，在修改的降压调节器电路内通过下拉开关机构的电流（Vx）或电流被感测到，其中下拉开关机构耦合到电感器的上游端 并且与电容器并联耦合。 计算下拉切换机制被禁用的目标时间（tlf），并且在计算的目标时间下拉下拉晶体管被禁用。
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