公开(公告)号：US20220292759A1

公开(公告)日：2022-09-15

申请号：US17749951

申请日：2022-05-20

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06T15/08 ,  G06F9/50 ,  G06T3/40 ,  G06T9/00 ,  G06T17/10

Abstract: Ray tracing hardware accelerators supporting motion blur and moving/deforming geometry are disclosed. For example, dynamic objects in an acceleration data structure are encoded with temporal and spatial information. The hardware includes circuitry that test ray intersections against moving/deforming geometry by applying such temporal and spatial information. Such circuitry accelerates the visibility sampling of moving geometry, including rigid body motion and object deformation, and its associated moving bounding volumes to a performance similar to that of the visibility sampling of static geometry.

公开(公告)号：US20200051318A1

公开(公告)日：2020-02-13

申请号：US16101232

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Ronald Charles BABICH, JR. ,  William Parsons NEWHALL, JR. ,  Peter NELSON ,  James ROBERTSON ,  John BURGESS

IPC: G06T15/06 ,  G06F9/38 ,  G06T17/00 ,  G06N5/04 ,  G06T1/20 ,  G06T1/60

Abstract: In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.

公开(公告)号：US20250095276A1

公开(公告)日：2025-03-20

申请号：US18962764

申请日：2024-11-27

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06F9/30 ,  G06F9/50 ,  G06T15/08 ,  G06T17/00

Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.

公开(公告)号：US20240355039A1

公开(公告)日：2024-10-24

申请号：US18761820

申请日：2024-07-02

Applicant: NVIDIA Corporation

Inventor： Samuli LAINE ,  Tero KARRAS ,  Timo AILA ,  Robert OHANNESSIAN ,  William Parsons NEWHALL, Jr. ,  Greg MUTHLER ,  Ian KWONG ,  Peter NELSON ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T15/005

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.

公开(公告)号：US20240095993A1

公开(公告)日：2024-03-21

申请号：US17946093

申请日：2022-09-16

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Magnus ANDERSSON ,  Ian KWONG ,  Edward BIDDULPH

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T15/005

Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.

公开(公告)号：US20240037841A1

公开(公告)日：2024-02-01

申请号：US18483762

申请日：2023-10-10

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06T15/08 ,  G06F9/50 ,  G06F9/30 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T15/08 ,  G06F9/5027 ,  G06F9/30094 ,  G06T17/005 ,  G06T2210/12

Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.

公开(公告)号：US20230084570A1

公开(公告)日：2023-03-16

申请号：US17946221

申请日：2022-09-16

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Henry Packard MORETON ,  Yury URALSKY ,  Levi OLIVER ,  Magnus ANDERSSON ,  Johannes DELIGIANNIS

IPC: G06T15/06 ,  G06T17/20

Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.

公开(公告)号：US20230081791A1

公开(公告)日：2023-03-16

申请号：US17946515

申请日：2022-09-16

Applicant: NVIDIA Corporation

Inventor： John BURGESS ,  Gregory MUTHLER ,  Nikhil DIXIT ,  Henry MORETON ,  Yury URALSKY ,  Magnus ANDERSSON ,  Marco SALVI ,  Christoph KUBISCH

IPC: G06T17/20 ,  G06T17/10 ,  G06T15/06 ,  G06T15/40

Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.

公开(公告)号：US20220383583A1

公开(公告)日：2022-12-01

申请号：US17885207

申请日：2022-08-10

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Ian Chi Yan KWONG

IPC: G06T15/06 ,  G06T15/08 ,  G06F9/50 ,  G06T17/20 ,  G06T17/10

Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure and its underlying primitives are disclosed. For example, traversal speed is improved by grouping processing of primitives sharing at least one figure (e.g., a vertex or an edge) during ray-primitive intersection testing. Grouping the primitives for ray intersection testing can reduce processing (e.g., projections and transformations of primitive vertices and/or determining edge function values) because at least a portion of the processing results related to the shared feature in one primitive can be used to determine whether the ray intersects another primitive(s). Processing triangles sharing an edge can double the culling rate of the triangles in the ray/triangle intersection test without replicating the hardware.

公开(公告)号：US20220165017A1

公开(公告)日：2022-05-26

申请号：US17669430

申请日：2022-02-11

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  James ROBERTSON ,  Magnus ANDERSON

IPC: G06T15/06 ,  G06T15/08 ,  G06T17/10 ,  G06T1/20 ,  G06F9/50 ,  G06T15/00

Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.