公开(公告)号：US07616500B2

公开(公告)日：2009-11-10

申请号：US11694989

申请日：2007-03-31

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting threshold voltage distributions and programs non-volatile storage elements to at least two ending threshold voltage distributions.

摘要翻译： 一组非易失性存储元件被擦除为擦除的阈值电压分布。 执行多遍编程处理，其将该非易失性存储元件组从擦除的阈值电压分布编程到设定的有效数据阈值电压分布。 每个编程遍具有一个或多个起始阈值电压分布，并将非易失性存储元件编程为至少两个结束阈值电压分布。

公开(公告)号：US07616495B2

公开(公告)日：2009-11-10

申请号：US11694991

申请日：2007-03-31

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process include programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process.

摘要翻译： 对多个非易失性存储元件执行多个编程处理。 编程过程中的每一个操作以使用程序脉冲将所述非易失性存储元件的至少一个子集编程到一组目标条件。 在一个实施例中，第一编程遍包括软编程，并且附加编程遍包括数据的编程。 在另一个实施例中，所有编程过程包括编程数据。 对于所述编程处理的至少一个子集，识别与实现相应编程处理的特定结果相关联的编程脉冲。 识别的编程脉冲用于调整随后编程过程的编程。

公开(公告)号：US07616490B2

公开(公告)日：2009-11-10

申请号：US11550383

申请日：2006-10-17

申请人： Nima Mokhlesi ,  Masaaki Higashitani

发明人： Nima Mokhlesi ,  Masaaki Higashitani

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/22

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621 ,  H01L21/28114 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7881

摘要： A select gate structure for a non-volatile storage system includes a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.

摘要翻译： 用于非易失性存储系统的选择栅极结构包括独立驱动的选择栅极和耦合电极。 耦合电极与NAND串中的字线相邻，并且具有施加的电压，其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。 特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。 当使用非相邻字线进行编程时，施加降低的电压。 电压也可以根据其他编程标准设定。 选择栅极由第一导电区域提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

公开(公告)号：US07615445B2

公开(公告)日：2009-11-10

申请号：US11534135

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：US07606079B2

公开(公告)日：2009-10-20

申请号：US11740091

申请日：2007-04-25

申请人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hock C. So

发明人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hock C. So

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5646

摘要： Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.

摘要翻译： 在读取操作期间通过在未选择的字线上提供减小的读取通过电压来减少非易失性存储设备中的功耗。 检查在其上正在读取存储元件的所选字线之后的一个或多个未选字线的编程状态，以确定未选择的字线是否包含编程的存储元件。 当识别出未编程的字线时，在该字线和在该字线之后的编程顺序中的其它字线提供减小的读通道电压。 编程状态可以通过例如存储在字线中的标志来确定，或者通过在最低读取状态下读取字线来确定。 被检查的未选择的字线可以在一组字线中预先确定，或者基于所选字线的位置自适应地确定。

公开(公告)号：US07532516B2

公开(公告)日：2009-05-12

申请号：US11771987

申请日：2007-06-29

申请人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu ,  Nima Mokhlesi ,  Deepak Chandra Sekar

发明人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu ,  Nima Mokhlesi ,  Deepak Chandra Sekar

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5634 ,  G11C2211/565

摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

摘要翻译： 一种非易失性存储装置，其中对具有负阈值电压的非易失性存储元件执行电流检测。 控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。 源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。 即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。 通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

公开(公告)号：US20090080265A1

公开(公告)日：2009-03-26

申请号：US11861571

申请日：2007-09-26

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

IPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5634

摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

摘要翻译： 非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线 第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块， 以及位于第二位置并连接到第二组位线的第二组感测模块。 第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。 第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

公开(公告)号：US20090080229A1

公开(公告)日：2009-03-26

申请号：US11861994

申请日：2007-09-26

申请人： Deepak Chandra Sekar ,  Nima Mokhlesi

发明人： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC分类号： G11C5/06 ,  H01L21/4763

CPC分类号： G11C16/0483 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76817 ,  H01L23/528 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are also formed from the same layer. Individual bit lines are formed having different thicknesses at different locations.

摘要翻译： 使用纳米压印光刻法在衬底上形成包括不同深度的沟槽的图案。 随后的金属沉积根据沟槽深度从单个金属层形成不同厚度的线。 从线路向下延伸的通道也由同一层形成。 在不同位置处形成具有不同厚度的各个位线。

公开(公告)号：US07508710B2

公开(公告)日：2009-03-24

申请号：US11558980

申请日：2006-11-13

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A method for operating non-volatile memory having boost structures. The boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.

摘要翻译： 一种用于操作具有升压结构的非易失性存储器的方法。 为单个NAND串提供升压结构，并且可以单独控制升压结构，以协助编程，验证和读取过程。 升压结构可以通常被提升和单独放电，部分地基于目标编程状态或验证电平。 升压结构有助于编程，从而可以减少字线上的编程和通过电压，从而减少诸如程序干扰的副作用。 在验证期间，可以同时验证字线上的所有存储元素。 升压结构也可以在阅读过程中有所帮助。 在一种方法中，NAND串具有双源极选择栅极，在该源极/漏极区域之间升压结构与衬底接触，并且经由NAND串的源极侧将升压电压提供给升压结构。

公开(公告)号：US07495962B2

公开(公告)日：2009-02-24

申请号：US11618569

申请日：2006-12-29

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/3418

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.

摘要翻译： 由于存储在相邻浮动栅极（或其他电荷存储元件）中的电荷的电场的耦合，可能会发生存储在非易失性存储单元的浮动栅极（或其他电荷存储元件）上的视在电荷的变化， 。 为了解决这种耦合，对于目标存储器单元的读取处理将向邻近的存储器单元（或其他存储单元）提供补偿，以便减少相邻存储单元对目标存储器单元具有的耦合效应。 所施加的补偿基于相邻存储单元的条件。 为了应用正确的补偿，读取过程将至少部分地将相邻存储器单元的读取操作与目标存储器单元的读取操作混合。