摘要:
An embodiment may include circuitry to determine whether to issue at least one credit to at least one sender of at least one packet. The credit(s) may be to grant permission to the at least one sender to issue the at least one packet to at least one receiver of the at least one packet. The determination of whether to issue the credit(s) may be based, at least in part, upon whether a time in which the at least one receiver is in a relatively lower power state prior to issuance of the credit(s) is at least sufficient to provide at least a predetermined amount of reduction in power consumption. The relatively lower power state may be relative to a relatively higher power state of the at least one receiver that prevails at the issuance of the credit(s). Additionally or alternatively, the circuitry may be to receive such credit(s).
摘要:
Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements.
摘要:
In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
摘要:
Methods and apparatus for provision of adaptive packet deflection to achieve fair, low-cost, and/or energy-efficient Quality of Service (QoS) in Network-on-Chip (NoC) devices are described. In some embodiments, it is determined whether a target port of a packet has reached a threshold utilization value and the packet is routed to an alternate port in response to a deflection probability value that is to be determined based on a utilization value of the target port and a priority level value of the packet. Other embodiments are also claimed and/or disclosed.
摘要:
The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.
摘要:
An embodiment may include circuitry to determine whether to issue at least one credit to at least one sender of at least one packet. The credit(s) may be to grant permission to the at least one sender to issue the at least one packet to at least one receiver of the at least one packet. The determination of whether to issue the credit(s) may be based, at least in part, upon whether a time in which the at least one receiver is in a relatively lower power state prior to issuance of the credit(s) is at least sufficient to provide at least a predetermined amount of reduction in power consumption. The relatively lower power state may be relative to a relatively higher power state of the at least one receiver that prevails at the issuance of the credit(s). Additionally or alternatively, the circuitry may be to receive such credit(s).
摘要:
An embodiment may include network controller to be comprised in a first node. The node may be communicatively coupled to a network and may include a host processor to execute an operating system environment. The operating system environment may include, at least in part, a communication protocol stack and an application. The circuitry may receive, at least in part, a packet from the network. The packet may include, at least in part, a header and payload. At least one portion of the payload may be associated with the application. The circuitry may issue at least one portion of the header to the stack. The circuitry may issue the at least one portion of the payload to a destination device in a manner that by-passes involvement of the stack. The destination device may be specified, at least in part, by the application. Many alternatives, variations, and modifications are possible.
摘要:
The present invention relates to platform power management. In some implementations, platform tasks, that require servicing by a host processor, may be serviced in groups to create longer or more idle periods to enable the host processor to be in lower power consuming states more often.
摘要:
Systems and methods may provide for determining an absolute energy break-even time for a first low power state with respect to a current state of a system. A relative energy break-even time may also be determined for the first low power state with respect to a second low power state based on at least in part the absolute energy break-even time. In addition, an operating state may be selected for the system based on at least in part the relative energy break-even time.
摘要:
An embodiment may include network controller to be comprised in a first node. The node may be communicatively coupled to a network and may include a host processor to execute an operating system environment. The operating system environment may include, at least in part, a communication protocol stack and an application. The circuitry may receive, at least in part, a packet from the network. The packet may include, at least in part, a header and payload. At least one portion of the payload may be associated with the application. The circuitry may issue at least one portion of the header to the stack. The circuitry may issue the at least one portion of the payload to a destination device in a manner that by-passes involvement of the stack. The destination device may be specified, at least in part, by the application. Many alternatives, variations, and modifications are possible.