利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

54 条记录 (耗时 0.018 秒)

    Transformer coupled quadrature tuned oscillator
    24.
    发明授权
    Transformer coupled quadrature tuned oscillator 失效
    变压器耦合正交调谐振荡器

    公开(公告)号：US06639481B1

    公开(公告)日：2003-10-28

    申请号：US10224684

    申请日：2002-08-20

    申请人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    发明人： Ashoke Ravi ,  Krishnamurthy Soumyanath

    IPC分类号： H03L700

    CPC分类号： H03L7/00

    摘要： First and second oscillator cells include tank circuits that may be tuned to a desired resonant frequency using varactors as variable reactance devices in a phase-shifting network. First and second transformers are connected to the oscillator cells to control the varactors.

    摘要翻译： 第一和第二振荡器单元包括可以使用变容二极管作为相移网络中的可变电抗装置来调谐到期望谐振频率的振荡电路。 第一和第二变压器连接到振荡器单元以控制变容二极管。

    Leakage-tolerant circuit and method for large register files
    25.
    发明授权
    Leakage-tolerant circuit and method for large register files 有权
    大容量寄存器文件的漏电电路及方法

    公开(公告)号：US06388940B1

    公开(公告)日：2002-05-14

    申请号：US09672177

    申请日：2000-09-27

    申请人： Atila Alvandpour ,  Ganesh Balamurugan ,  Krishnamurthy Soumyanath

    发明人： Atila Alvandpour ,  Ganesh Balamurugan ,  Krishnamurthy Soumyanath

    IPC分类号： G11C800

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.

    摘要翻译： 一种新颖的电路技术，用于减小通过大寄存器堆的读路径的漏电流，其中在栅极读取晶体管和局部位线之间的临界传输晶体管上施加负栅极 - 源极电压，使得当单元处于第一 状态，来自单元读取晶体管的动态节点的漏电流减小。 减小的漏电流增加了读操作的鲁棒性和性能。

    Soft error rate tolerant latch
    26.
    发明授权
    Soft error rate tolerant latch 有权
    软错误率容错锁存器

    公开(公告)号：US06380781B1

    公开(公告)日：2002-04-30

    申请号：US09430977

    申请日：1999-11-01

    申请人： Tanay Karnik ,  Krishnamurthy Soumyanath ,  Shekhar Y. Borkar

    发明人： Tanay Karnik ,  Krishnamurthy Soumyanath ,  Shekhar Y. Borkar

    IPC分类号： H03K312

    CPC分类号： G01R31/318525 ,  G01R31/31816

    摘要： A latch having increased soft error rate tolerance includes cross-coupled inverters having transistors with varying sizes. Diffusion regions of transistors coupled to storage nodes are kept small to reduce the effect of charge accumulation resulting from particles bombarding the bulk of an integrated circuit die. Transistors having gates coupled to the storage nodes are increased in size to increase the capacitance on the storage nodes. The reduced size of diffusion regions and increased size of gates on storage nodes combine to reduce the effects of accumulated charge. Diffusion region area is further reduced by reducing the size of pass gates that load normal data and scan data. A large capacitor is coupled to a feedback node within the cross-coupled inverters to further reduce the effect of accumulated charge.

    摘要翻译： 具有增加的软错误率容限的锁存器包括具有不同尺寸的晶体管的交叉耦合反相器。 耦合到存储节点的晶体管的扩散区域保持较小，以减少由颗粒轰击集成电路管芯的体积而产生的电荷累积的影响。 具有耦合到存储节点的栅极的晶体管的尺寸增加以增加存储节点上的电容。 扩散区尺寸减小，存储节点栅极尺寸增大，减少了累积电荷的影响。 通过减小加载正常数据和扫描数据的通孔的大小进一步减小扩散区域面积。 大电容器耦合到交叉耦合的反相器内的反馈节点，以进一步降低累积电荷的影响。

    Differential circuits employing forward body bias
    27.
    发明授权
    Differential circuits employing forward body bias 失效
    采用正向偏置的差分电路

    公开(公告)号：US06218892B1

    公开(公告)日：2001-04-17

    申请号：US09256842

    申请日：1999-02-24

    申请人： Krishnamurthy Soumyanath ,  Ali Keshavarzi ,  Vivek K. De ,  Shekhar Y. Borkar

    发明人： Krishnamurthy Soumyanath ,  Ali Keshavarzi ,  Vivek K. De ,  Shekhar Y. Borkar

    IPC分类号： G05F110

    CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948 ,  H03L7/0812 ,  H03L7/0995

    摘要： In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.

    摘要翻译： 在一些实施例中，本发明包括具有差分放大器和体偏置控制电路的电路。 差分放大器包括第一和第二FET晶体管的差分对，以响应于输入电压信号至少部分地控制输出电压信号，第一和第二FET晶体管被配置为匹配并具有主体。 体偏置控制电路向身体提供体偏置电压信号，以将第一和第二FET晶体管置于正向体偏置状态。 差分放大器和体偏置电路可用于读出放大器，比较器，压控振荡器，延迟锁定环路和锁相环路以及其他电路。

    Low loss interconnect structure for use in microelectronic circuits
    29.
    发明授权
    Low loss interconnect structure for use in microelectronic circuits 有权
    用于微电子电路的低损耗互连结构

    公开(公告)号：US07352059B2

    公开(公告)日：2008-04-01

    申请号：US11152643

    申请日：2005-06-14

    申请人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

    发明人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

    IPC分类号： H01L27/10 ,  H01L23/52 ,  H01L23/522 ,  H01R12/00

    CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

    摘要翻译： 低损耗管芯互连结构包括在微电子管芯的金属层之一上的第一和第二差分信号线。 还可以在与差分信号线不平行（例如，正交））的管芯的另一金属层上提供一个或多个迹线。 由于迹线不平行，它们为差分信号线上的信号提供了相对较高的阻抗返回路径。 因此，通过相反的微分线路的信号返回路径对于差分线路上的信号占优势。 在一个应用中，低损耗互连结构用于管芯内的相关时钟分配网络。