摘要:
Disclosed herein are circuits, devices and methods that address challenges associated with power amplifier systems. A power amplifier system includes two or more fast error amplifiers coupled to corresponding power amplifiers. The fast error amplifiers are configured to generate envelope tracking signals based on a signal envelope, the envelope tracking signals modifying a DC-DC regulated voltage from a DC-DC converter to more efficiently operate the power amplifiers. By splitting the envelope tracking between two or more fast error amplifiers and amplification between corresponding two or more power amplifiers, the power, frequency or bandwidth, linearity, signal-to-noise ratio, efficiency, or the like of the power amplifier system can be improved. Wireless communications configurations with such power amplifier systems can provide uplink carrier aggregation and/or cellular signals based on standards and protocols that require increased bandwidth and/or power.
摘要:
Front-end systems for a transmitter included in a radio device are disclosed. An example front-end system may comprise a voltage-to-power mixer. The voltage-to-power mixer may be configured to up-convert a baseband signal to a high-frequency signal by multiplying the baseband signal with a local oscillator signal. Additionally, the voltage-to-power mixer may include a voltage feedback circuit. The example front-end system may further comprise a two-stage power amplifier. The two-stage power amplifier may be configured to amplify the high-frequency signal.
摘要:
A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.
摘要:
A transmitter for transmitting a transmission signal is disclosed. The transmitter includes: a gain stage, for receiving an input signal and amplifying the input signal according to a gain to generate an amplified signal; and an output stage, coupled to the gain stage, for receiving a first reference voltage signal and the amplified signal and utilizing the first reference voltage signal to perform a predetermined operation on the amplified signal to generate the output signal.
摘要:
In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.
摘要:
A differential to single-ended converter, which is composed of a transconductance amplifier, a current mirror and buffer circuit and a transimpedance stage, is disclosed. A differential voltage signal is provided to the inputs of the transconductance amplifier and converted to a differential current signal. The current mirror and buffer circuit serves as a differential to single-ended current conveyer and isolates the transconductance stage and the following transimpedance stage. Finally, the single-ended current signal is provided to the input of the transimpedance stage and converted to a single-ended current signal.
摘要:
A folded cascade voltage gain cell is implemented in a single stage by collapsing p-channel transistor branches receiving output currents from two sets of n-channel transistor branches and producing the output voltage into a single set of branches, summing the output currents from two sets of n-channel transistor branches in a single pair of nodes. While power consumption is only slightly improved over multistage folded cascade voltage gain cells, the circuit is implemented with fewer transistors and is therefore smaller and more reliable. Moreover, because only one gain stage is employed with a smaller number of internal nodes, the circuit's operation contains a smaller number of poles, and bandwidth is improved.
摘要:
A circuit comprises: a circuit input; a circuit output; at least one passive feedback loop coupled between the circuit output and the circuit input; an active element, coupled in a feed-forward path of the circuit between the circuit input and the circuit output and configured to drive the at least one feedback loop in order to establish a function of the circuit, wherein the feed-forward path of the circuit comprises a second node (Vx) and a first node which are internal nodes of the active element and which are coupled between the circuit input and the circuit output, wherein the first node is configured to have a first voltage, the first voltage being a function of the circuit output, wherein the active element comprises a first voltage drop element coupled between the second node (Vx) and the first node.
摘要:
A low noise amplifier includes: first and seventh transistors configured to respectively receive first and second input signals; second, third, and fifth transistors connected to the first transistor; eighth, ninth, and eleventh transistors connected to the seventh transistor; a third resistive element; fourth and tenth transistors respectively connected to the third and ninth transistors; sixth and twelfth transistors respectively connected to second and first output terminals; and first and second resistive elements.
摘要:
Methods and devices for eliminating a systematic imbalance and reducing variations in circuit parameters for a high gain amplifies. A bias generator having a copy of an actual amplifier branch and an already generated bias voltage can be added to the amplifier to generate a bias voltage for a final current source at a current summing node so as to eliminate systematic imbalance in the bias current. A high impedance node can be wired in the bias generator such that all devices in the bias generator are in saturation across, for example, PVT (Process, Voltage and Temperature) corners in order to minimize tracking errors. A degeneration transistor similar to a differential pair element can be split into two equal halves.