-
公开(公告)号：US10713136B2
公开(公告)日：2020-07-14
申请号：US15713557
申请日：2017-09-22
Applicant: QUALCOMM Incorporated
Inventor： Fahad Ahmed , Chulmin Jung , Sei Seung Yoon , Esin Terzioglu
Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.
-
22.发明授权公开(公告)号：US08958226B2
公开(公告)日：2015-02-17
申请号：US13730524
申请日：2012-12-28
Applicant: Qualcomm Incorporated
Inventor： Esin Terzioglu , Nishith Desai , Rakesh Vattikonda , ChangHo Jung , Sei Seung Yoon
CPC classification number: G11C15/04 , G11C15/00 , G11C15/043 , G11C15/046
Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.
Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。
-
公开(公告)号：US08908464B2
公开(公告)日：2014-12-09
申请号：US13765559
申请日：2013-02-12
Applicant: QUALCOMM Incorporated
Inventor： Gregory Ameriada Uvieghara , Michael Batenburg , Esin Terzioglu , Yucong Tao
CPC classification number: G11C5/143 , G01R31/31719 , G01R31/3658 , G11C7/24
Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.
Abstract translation: 用于检测与集成电路上的次正常读取电压相关的电源攻击的系统和方法。 在启动集成电路的电源并且在从非易失性存储器（NVM）读取配置信息之前，首先读取与NVM相关联的测试单元。 测试单元与NVM共用公共电源，并且当在公共电源上施加次正常读取电压时，来自测试单元的输出读取值被配置为偏离测试单元中预编程的值。 因此，通过将输出读取值与预编程值进行比较，可以确定公共电源的电压是否是次正常，其中配置信息将在非正常读取电压下读取不正确。 如果电压低于正常值，则上电将中止。 否则，可以通过从NVM读取配置信息来上电。
-
公开(公告)号：US08836040B2
公开(公告)日：2014-09-16
申请号：US13671114
申请日：2012-11-07
Applicant: QUALCOMM Incorporated
Inventor： Pratyush Kamal , Esin Terzioglu , Foua Vang , Prayag Bhanubhai Patel , Giridhar Nallapati , Animesh Datta
IPC: H01L21/70 , H01L21/8238 , H01L29/66 , H01L27/118 , H01L27/02 , H01L27/092
CPC classification number: H01L27/092 , H01L27/0207 , H01L27/11807 , H01L29/66545 , H01L2027/11831
Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.
Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域的上方，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。
-
公开(公告)号：US20140226426A1
公开(公告)日：2014-08-14
申请号：US13765559
申请日：2013-02-12
Applicant: QUALCOMM INCORPORATED
Inventor： Gregory Ameriada Uvieghara , Michael Batenburg , Esin Terzioglu , Yucong Tao
IPC: G11C5/14
CPC classification number: G11C5/143 , G01R31/31719 , G01R31/3658 , G11C7/24
Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.
Abstract translation: 用于检测与集成电路上的次正常读取电压相关的电源攻击的系统和方法。 在启动集成电路的电源并且在从非易失性存储器（NVM）读取配置信息之前，首先读取与NVM相关的测试单元。 测试单元与NVM共用公共电源，并且当在公共电源上施加次正常读取电压时，来自测试单元的输出读取值被配置为偏离测试单元中预编程的值。 因此，通过将输出读取值与预编程值进行比较，可以确定公共电源的电压是否是次正常，其中配置信息将在非正常读取电压下读取不正确。 如果电压低于正常值，则上电将中止。 否则，可以通过从NVM读取配置信息来上电。
-
Patent Agency Ranking
26.发明授权Method and semiconductor apparatus for reducing power when transmitting data between devices in the semiconductor apparatus 有权用于在半导体装置中的器件之间传输数据时降低功率的方法和半导体装置公开(公告)号：US09071239B2
公开(公告)日：2015-06-30
申请号：US13799686
申请日：2013-03-13
Applicant: QUALCOMM Incorporated
Inventor： Chulmin Jung , Sei Seung Yoon , Esin Terzioglu , Hari Ananthanarayanan , Venugopal Boynapalli
CPC classification number: H03K17/002 , G11C7/02 , G11C7/10 , G11C7/1006
Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.
Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。
-
公开(公告)号：US09036446B2
公开(公告)日：2015-05-19
申请号：US13663042
申请日：2012-10-29
Applicant: QUALCOMM Incorporated
Inventor： Esin Terzioglu , Changho Jung , Shahzad Nazar , Balachander Ganesan , Alex Dongkyu Park
CPC classification number: G11C8/10
Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.
Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。
-
公开(公告)号：US08934278B2
公开(公告)日：2015-01-13
申请号：US13730487
申请日：2012-12-28
Applicant: QUALCOMM Incorporated
Inventor： Rakesh Vattikonda , Nishith Desai , ChangHo Jung , Sei Seung Yoon , Esin Terzioglu
Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.
Abstract translation: 混合三元内容可寻址存储器（TCAM）内的方法包括将搜索词的第一部分与第一TCAM级中的存储字的第一部分进行比较。 该方法还包括将第一TCAM级的输出与第二TCAM级的输入进行接口。 该方法还包括当搜索词的第一部分与存储的单词的第一部分匹配时，在第二TCAM阶段中将搜索词的第二部分与所存储的单词的第二部分进行比较。 第一个TCAM阶段与第二个TCAM阶段不同。
-
公开(公告)号：US08830779B1
公开(公告)日：2014-09-09
申请号：US13924916
申请日：2013-06-24
Applicant: QUALCOMM Incorporated
Inventor： Esin Terzioglu , Gregory Ameriada Uvieghara , Sei Seung Yoon , Balachander Ganesan , Anil Chowdary Kota
Abstract: A fuse-based memory includes a plurality of bit lines. Each bit lines couples to a corresponding plurality of fuses. The fuses couple to ground through corresponding access transistors. The memory is configured to precharge an accessed one of the bit lines and a reference one of the bit lines using a low voltage supply. In contrast, a resulting voltage difference between the accessed bit line and the reference bit line is sensed using a sense amplifier powered by a high voltage supply, wherein a high voltage supplied by the high power supply is greater than a low voltage supplied by the low voltage supply.
Abstract translation: 基于熔丝的存储器包括多个位线。 每个位线耦合到相应的多个保险丝。 保险丝通过相应的存取晶体管耦合到地。 存储器被配置为使用低电压电源对所访问的位线之一和位线中的参考一个进行预充电。 相比之下，使用由高压电源供电的读出放大器来感测访问的位线和参考位线之间产生的电压差，其中由高电源提供的高电压大于由低电压提供的低电压 电压供应
-
公开(公告)号：US20140124868A1
公开(公告)日：2014-05-08
申请号：US13671114
申请日：2012-11-07
Applicant: QUALCOMM INCORPORATED
Inventor： Pratyush Kamal , Esin Terzioglu , Foua Vang , Prayag Bhanubhai Patel , Giridhar Nallapati , Animesh Datta
IPC: H01L27/092 , H01L29/66
CPC classification number: H01L27/092 , H01L27/0207 , H01L27/11807 , H01L29/66545 , H01L2027/11831
Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.
Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域之上，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。
-
-
-
-
-
-
-
-
-
Search Results
31
records
(took 0.017 seconds)
