公开(公告)号：US20180059975A1

公开(公告)日：2018-03-01

申请号：US15245725

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Keith Alan Bowman ,  Yu Pu ,  Francois Ibrahim Atallah

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F3/0625 ,  G06F1/324 ,  G06F1/3262 ,  G06F1/3275 ,  G06F3/0629 ,  G06F3/0673 ,  G11C5/14 ,  G11C5/147 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  Y02D10/14

Abstract: Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memory elements. Based on this reported information, a controller ascertains an appropriate power level to insure a proper data retention voltage (DRV) is applied on voltage rails by a power management unit (PMU) circuit. By using the proper DRV based on the speed characteristics of the sub-elements within the memory elements, power conservation is achieved.

公开(公告)号：US09842634B2

公开(公告)日：2017-12-12

申请号：US14862555

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C8/08 ,  G11C11/419 ,  G11C11/413 ,  G11C15/04 ,  G11C7/12

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413 ,  G11C11/419 ,  G11C15/04

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

公开(公告)号：US09625924B2

公开(公告)日：2017-04-18

申请号：US14860717

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Hoan Huu Nguyen ,  Keith Alan Bowman ,  Yeshwant Nagaraj Kolla ,  Burt Lee Price ,  Samantak Gangopadhyay

IPC: G05F1/56

CPC classification number: G05F1/56 ,  H03K19/0008

Abstract: Systems and methods relate to a low-dropout voltage (LDO) voltage regulator which receives a maximum supply voltage and provides a regulated voltage to a load, where the load may be a processing core of a multi-core processing system. A leakage current supply source includes a leakage current sensor to determine a leakage current demand of the load of the LDO voltage regulator and a leakage current supply circuit to supply the leakage current demand. In this manner, the leakage current supply source provides current assistance to the LDO voltage regulator, such that the LDO voltage regulator can supply only dynamic current. Thus, headroom voltage of the LDO voltage regulator, which is a difference between the maximum supply voltage and the regulated voltage, can be reduced. Reducing the headroom voltage allows greater number of dynamic voltage and frequency scaling states of the load.

公开(公告)号：US11270761B2

公开(公告)日：2022-03-08

申请号：US17223764

申请日：2021-04-06

Applicant: Qualcomm Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Daniel Yingling ,  Jihoon Jeong ,  Yu Pu

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US10978139B2

公开(公告)日：2021-04-13

申请号：US16431503

申请日：2019-06-04

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Daniel Yingling ,  Jihoon Jeong ,  Yu Pu

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/10 ,  G11C11/417 ,  G11C11/419 ,  G11C11/418

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US10658029B2

公开(公告)日：2020-05-19

申请号：US16138174

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  Hari Rao

IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/419 ,  G11C11/408 ,  G11C8/08 ,  G11C8/10 ,  G11C16/26

Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.

公开(公告)号：US10224084B2

公开(公告)日：2019-03-05

申请号：US15717028

申请日：2017-09-27

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C15/04 ,  G11C5/14 ,  G11C29/00 ,  G11C7/12 ,  G11C8/08

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

公开(公告)号：US10026456B2

公开(公告)日：2018-07-17

申请号：US14862579

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C11/00 ,  G11C5/14 ,  G11C11/419 ,  G11C11/413 ,  G11C15/04 ,  G11C7/12 ,  G11C8/08

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

公开(公告)号：US20180033465A1

公开(公告)日：2018-02-01

申请号：US15717028

申请日：2017-09-27

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C5/14 ,  G11C11/419 ,  G11C7/12 ,  G11C11/413 ,  G11C8/08 ,  G11C15/04

CPC classification number: G11C11/00 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413 ,  G11C11/419 ,  G11C15/04 ,  G11C29/00

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

公开(公告)号：US20170316838A1

公开(公告)日：2017-11-02

申请号：US15645355

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C11/00

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.