公开(公告)号：US20230118028A1

公开(公告)日：2023-04-20

申请号：US17451302

申请日：2021-10-18

Applicant: QUALCOMM Incorporated

Inventor： Michelle Yejin Kim ,  Kuiwon Kang ,  Joan Rey Villarba Buot ,  Ching-Liou Huang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Integrated circuit (IC) packages employing a supplemental metal layer with coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch, and related fabrication methods. An IC package includes a semiconductor die (“die”) electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer adjacent to and coupled to the die. To reduce or avoid metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, a supplemental metal layer with additional metal interconnects is disposed adjacent to the die-size ETS metallization layer. The additional metal interconnects are coupled in a vertical direction to the embedded metal traces in the die-side ETS metallization layer to increase metal density of die-side metal interconnects formed by the additional metal interconnects coupled to the embedded metal traces in the die-side ETS metallization layer.

公开(公告)号：US11545439B2

公开(公告)日：2023-01-03

申请号：US17017418

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00

Abstract: A package that includes a substrate and an integrated device. The substrate includes a core portion, a first substrate portion and a second substrate portion. The core portion includes a core layer and core interconnects. The first substrate portion is coupled to the core portion. The first substrate portion includes at least one first dielectric layer coupled to the core layer, and a first plurality of interconnects located in the at least one first dielectric layer. The second substrate portion is coupled to the core portion. The second substrate includes at least one second dielectric layer coupled to the core layer, and a second plurality of interconnects located in the at least one second dielectric layer. The core portion and the second substrate portion include a cavity. The integrated device is coupled to the first substrate portion through the cavity of the second substrate portion and the core portion.

公开(公告)号：US11527498B2

公开(公告)日：2022-12-13

申请号：US17038124

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Michelle Yejin Kim ,  Marcus Hsu

IPC: H01L23/00

Abstract: Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.

公开(公告)号：US11437335B2

公开(公告)日：2022-09-06

申请号：US16921152

申请日：2020-07-06

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Aniket Patil ,  Bohan Yan ,  Dongming He

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/367

Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation. The dielectric layer in the package substrate may also include dielectric materials having different thermal conductivities to further facilitate thermal dissipation and/or desired electrical or mechanical characteristics.

公开(公告)号：US20220037257A1

公开(公告)日：2022-02-03

申请号：US17158374

申请日：2021-01-26

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Michelle Yejin Kim ,  Joan Rey Villarba Buot ,  Jialing Tong

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

公开(公告)号：US10651160B2

公开(公告)日：2020-05-12

申请号：US15867518

申请日：2018-01-10

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Houssam Jomaa ,  Christopher Bahr ,  Layal Rouhana

IPC: H01L21/48 ,  H01L23/49 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

Abstract: A package that includes a substrate comprising an interposer interconnect and a cavity, a redistribution portion coupled to the substrate, the redistribution comprising a plurality of redistribution interconnects, and a first die coupled to the redistribution portion through the cavity of the substrate. A substantial region between a side surface of the first die and the substrate is free of an encapsulation layer. In some implementations, the substrate is free of a metal ring that surrounds the first die. In some implementations, the redistribution portion comprises a barrier layer and a first interconnect coupled to the barrier layer. The barrier layer is coupled to the interposer interconnect.

公开(公告)号：US10157824B2

公开(公告)日：2018-12-18

申请号：US15678698

申请日：2017-08-16

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Houssam Jomaa ,  Layal Rouhana ,  Seongryul Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

公开(公告)号：US11791320B2

公开(公告)日：2023-10-17

申请号：US17456068

申请日：2021-11-22

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Joan Rey Villarba Buot ,  Michelle Yejin Kim ,  Kuiwon Kang ,  Aniket Patil

IPC: H01L25/10 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L25/50 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods. To facilitate providing a reduced thickness substrate in the IC package to reduce overall height of the IC package while supporting higher density input/output (I/O) connections, a package substrate in the IC package includes a double side ETS. A double side ETS includes two (2) adjacent ETS metallization layers that both include metal traces embedded in an insulating layer. The embedded metal traces in the ETS metallization layers of the double side ETS can be electrically coupled to each other through vertical interconnect accesses (vias) (e.g., metal pillars, metal posts) to provide signal routing paths between embedded metal traces in the ETS metallization layers.

公开(公告)号：US11676905B2

公开(公告)日：2023-06-13

申请号：US17158374

申请日：2021-01-26

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Michelle Yejin Kim ,  Joan Rey Villarba Buot ,  Jialing Tong

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/92227 ,  H01L2225/06568

Abstract: An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

公开(公告)号：US20230163112A1

公开(公告)日：2023-05-25

申请号：US17456068

申请日：2021-11-22

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Joan Rey Villarba Buot ,  Michelle Yejin Kim ,  Kuiwon Kang ,  Aniket Patil

IPC: H01L25/10 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L25/50 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107

Abstract: Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods. To facilitate providing a reduced thickness substrate in the IC package to reduce overall height of the IC package while supporting higher density input/output (I/O) connections, a package substrate in the IC package includes a double side ETS. A double side ETS includes two (2) adjacent ETS metallization layers that both include metal traces embedded in an insulating layer. The embedded metal traces in the ETS metallization layers of the double side ETS can be electrically coupled to each other through vertical interconnect accesses (vias) (e.g., metal pillars, metal posts) to provide signal routing paths between embedded metal traces in the ETS metallization layers.