公开(公告)号：US09852104B2

公开(公告)日：2017-12-26

申请号：US14626847

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4295

Abstract: A device is provided comprising a bus, a first set of devices, and a second set of devices. The first set of devices is coupled to the bus and configured to communicate over the bus according to a first communication protocol. The second set of devices is coupled to the bus and configured to communicate over the bus according to both the first communication protocol and a second communication protocol. In a first mode of operation, the first set of devices and second set of devices may concurrently communicate over the bus using the first communication protocol. In a second mode of operation, the second set of devices communicate with each other using the second communication protocol over the bus, and the first set of devices to stop operating on the bus.

公开(公告)号：US09755818B2

公开(公告)日：2017-09-05

申请号：US14491884

申请日：2014-09-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H04L7/04 ,  H04L7/033 ,  H04L25/14 ,  H04L7/027

CPC classification number: H04L7/0087 ,  H04L7/0008 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

公开(公告)号：US09710423B2

公开(公告)日：2017-07-18

申请号：US14243459

申请日：2014-04-02

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42 ,  G06F13/364 ,  H04L12/64

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L12/6418

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

公开(公告)号：US09678828B2

公开(公告)日：2017-06-13

申请号：US14511160

申请日：2014-10-09

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F11/10 ,  G06F13/42 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F13/4221 ,  H03M13/096

Abstract: A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission.

公开(公告)号：US20160380755A1

公开(公告)日：2016-12-29

申请号：US15262280

申请日：2016-09-12

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/14 ,  H04L7/04

CPC classification number: H04L7/0087 ,  H04L7/0008 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

公开(公告)号：US09490964B2

公开(公告)日：2016-11-08

申请号：US14555097

申请日：2014-11-26

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L27/10 ,  H03D13/00 ,  H04L7/00 ,  H04L7/04 ,  H04L7/08 ,  G11C8/06 ,  G06F13/40 ,  H04L7/033 ,  H04L25/14 ,  H04L25/49

CPC classification number: H04L7/0087 ,  G06F13/4072 ,  G11C8/06 ,  H04L7/0037 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/042 ,  H04L7/08 ,  H04L25/14 ,  H04L25/49

Abstract: A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal.

Abstract translation: 提供了一种方法和装置。 该装置可以包括具有比较器的时钟恢复电路，该比较器提供指示输入信号是否匹配输入信号的电平锁存实例的比较信号，提供比较信号的滤波版本的第一设置复位锁存器，其中 第一设置复位锁存器由比较信号的第一次有效转换设置，并且不受在预定时间段期间发生的比较信号的进一步转换的影响，接收比较信号的滤波版本的延迟电路和输出 第一时钟信号上的第一脉冲和第二设置复位锁存器，其被配置为当第一时钟信号上存在第一脉冲时，在输出时钟信号上提供第二脉冲，并且比较信号指示电平锁存的实例 输入信号与输入信号不匹配。

公开(公告)号：US09444612B2

公开(公告)日：2016-09-13

申请号：US14834219

申请日：2015-08-24

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: H04L7/00 ,  H04L7/027 ,  G06F13/40 ,  G06F13/42 ,  H04L25/14 ,  H04L25/00

CPC classification number: H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

公开(公告)号：US09426082B2

公开(公告)日：2016-08-23

申请号：US14577897

申请日：2014-12-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04B1/38 ,  H04L12/801 ,  H04L7/033 ,  H04L25/49 ,  H04L25/493

CPC classification number: H04L47/34 ,  H04L7/033 ,  H04L25/4906 ,  H04L25/493

Abstract: Systems, methods and apparatus are described for use in a communications link having a number of connectors. A method for communication using differential signaling with symbol transition clocking signaling communicates symbols over a communications link without transmitting a clock signal in a dedicated lane of the communications link. At a receiver, clock information may be extracted without using a phase-locked loop. The method includes converting data bits into a plurality of transition numbers, converting the plurality of transition numbers into a sequence of symbols, and transmitting the sequence of symbols over a plurality of signal wires. A clock signal may be embedded in transitions between consecutive symbols in the sequence of symbols. Each consecutive pair of transition numbers in the plurality of transition numbers may include two transition numbers that are different from one another. The sequence of symbols may be transmitted as a plurality of differential signals.

Abstract translation: 描述了用于具有多个连接器的通信链路中的系统，方法和装置。 一种使用具有符号转换时钟信令的差分信令的通信方法通过通信链路传送符号，而不在通信链路的专用通道中传送时钟信号。 在接收机处，可以提取时钟信息而不使用锁相环。 该方法包括将数据比特转换成多个转换号码，将多个转换号码转换为符号序列，以及通过多条信号线发送符号序列。 时钟信号可以嵌入在符号序列中的连续符号之间的转换中。 多个转移号码中的每个连续的一对转移号码可以包括彼此不同的两个转换号码。 符号序列可以作为多个差分信号发送。

公开(公告)号：US20160127121A1

公开(公告)日：2016-05-05

申请号：US14992450

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L7/027 ,  H04L25/493 ,  H04L25/02

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential number from a set of sequential numbers. The sequential number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换号码都从一组连续号码转换为一个顺序号码。 顺序号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播分散在多条n线上，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为序列号可保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零差分电压。

公开(公告)号：US20160065357A1

公开(公告)日：2016-03-03

申请号：US14939692

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H04L25/02 ,  H04L7/033

CPC classification number: H04L7/0008 ,  H04L7/0066 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/0272

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multilane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 从在多通道接口的第一通道上发送的第一符号序列提取的时钟用于接收和解码第一符号序列，并且接收和解码在多路接口的第二通道上发送的数据和/或符号 。 时钟信号可以从第一符号序列中的连续符号对之间的N条线路的信令状态的转换导出。 第一条车道可以使用N！ 编码和第二个通道可能是串行或N！ 链接。