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    FLOW CONTROL PROTOCOL FOR AN AUDIO BUS
    22.
    发明申请
    FLOW CONTROL PROTOCOL FOR AN AUDIO BUS 审中-公开

    公开(公告)号：US20180018296A1

    公开(公告)日：2018-01-18

    申请号：US15632519

    申请日：2017-06-26

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio

    IPC: G06F13/42 ,  G06F3/16

    CPC classification number: G06F13/4282 ,  G06F3/162 ,  H04L12/43 ,  H04L12/4625

    Abstract: A flow control protocol for an audio bus is disclosed. In an exemplary aspect, an audio source may push content to an audio sink over one or more cascaded audio bus segments or links. The audio source will send an indication to the audio sink that data is coming, and the audio sink should manipulate the data accordingly. Conversely, the audio source may also send an indication to the audio sink that, in a particular sample-event in a particular future sample-window, no data is present and the audio sink may disregard any bits in the corresponding sample-event. In another exemplary aspect, the audio sink may request data from the audio source with a receive ready indication. The audio source then sends data in a corresponding time slot for processing by the audio sink. Likewise, the audio sink may provide an indication that the audio sink cannot accept more data through a negative receive ready indication.

    Control circuits for generating output enable signals, and related systems and methods
    24.
    发明授权
    Control circuits for generating output enable signals, and related systems and methods 有权

    公开(公告)号：US09658645B2

    公开(公告)日：2017-05-23

    申请号：US14713058

    申请日：2015-05-15

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio ,  Meysam Azin ,  Alexander Khazin ,  Le Wang

    IPC: G06F1/00 ,  G06F1/10 ,  G06F13/42 ,  G06F1/06

    CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F13/4291

    Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

    Delay circuits and related systems and methods
    25.
    发明授权
    Delay circuits and related systems and methods 有权
    延时电路及相关系统及方法

    公开(公告)号：US09520865B2

    公开(公告)日：2016-12-13

    申请号：US14477367

    申请日：2014-09-04

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio ,  Alexander Golubitski ,  Haim Hagay Haller ,  Felix Kolmakov ,  Gilad Sthoeger

    IPC: G06F1/12 ,  H03K5/13 ,  G11C19/00 ,  G06F13/40 ,  G06F13/42 ,  G06F1/10 ,  H03K5/00

    CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

    Abstract translation: 公开了延迟电路及相关的系统和方法。 在一个方面，提供延迟电路，其使用逻辑来精确地延迟输出使能信号，以减少或避免从设备内的数据危害。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟接收信号中的输出使能。 第一移位寄存器链由快速时钟的上升沿提供时钟，并提供第一个选通信号。 第二移位寄存器链由快速时钟的负沿计时，并提供第二选通信号。 该逻辑使用第一和第二选通信号，以及信号中的输出使能，以提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度准确的时间延迟，以减少或避免一个区域的数据危害和功率有效的方式。

    FULL BANDWIDTH COMMUNICATION BUSES
    26.
    发明申请
    FULL BANDWIDTH COMMUNICATION BUSES 有权
    全带宽通信总线

    公开(公告)号：US20160259743A1

    公开(公告)日：2016-09-08

    申请号：US15059009

    申请日：2016-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio ,  Boaz Moskovich ,  Michael Zilbershtein

    IPC: G06F13/36 ,  G06F13/42

    CPC classification number: G06F13/36 ,  G06F13/4282 ,  G06F13/4291 ,  H04L47/72 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Full bandwidth communication buses are disclosed. While primarily focused on the Serial Low-power Inter-chip Media Bus (SLIMbus) communication bus, the concepts of the present disclosure may be extended to other communication buses. Exemplary aspects of the present disclosure utilize a reserved segment distribution code and a segment length to define a Segment Interval that is better-sized relative to raw data bits. By fitting the segment interval to the size of the raw data bits, bandwidth utilization is maximized, resulting in faster effective data transfers. Completion of such efficient data transfers may allow the communication bus to spend more time in a low-power mode and thus, conserve power. Additionally, such efficient data transfers may allow for better quality in presentation of multimedia content to the user.

    Abstract translation: 全带宽通信总线被公开。 虽然主要关注于串行低功率片上媒体总线（SLIMbus）通信总线，但是本公开的概念可以扩展到其他通信总线。 本公开的示例性方面利用保留段分布代码和段长度来定义相对于原始数据位更好的段间隔。 通过将段间隔拟合为原始数据位的大小，带宽利用率最大化，从而实现更快的有效数据传输。 完成这种有效的数据传输可以允许通信总线在低功率模式下花费更多的时间，从而节省功率。 此外，这种有效的数据传输可以允许在向用户呈现多媒体内容方面更好的质量。

    DEVICE IDENTIFICATION GENERATION IN ELECTRONIC DEVICES TO ALLOW EXTERNAL CONTROL OF DEVICE IDENTIFICATION FOR BUS COMMUNICATIONS IDENTIFICATION, AND RELATED SYSTEMS AND METHODS
    27.
    发明申请
    DEVICE IDENTIFICATION GENERATION IN ELECTRONIC DEVICES TO ALLOW EXTERNAL CONTROL OF DEVICE IDENTIFICATION FOR BUS COMMUNICATIONS IDENTIFICATION, AND RELATED SYSTEMS AND METHODS 审中-公开
    电子设备中的设备识别生成允许用于总线通信的设备识别的外部控制识别及相关系统和方法

    公开(公告)号：US20150220475A1

    公开(公告)日：2015-08-06

    申请号：US14609488

    申请日：2015-01-30

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio ,  Yossi Amon ,  Nir Gerber ,  Assaf Shacham

    IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

    CPC classification number: G06F13/4221 ,  G06F13/364 ,  G06F13/409 ,  G06F13/4282 ,  G06F13/4291 ,  H04L61/2038 ,  H04L61/2046 ,  H04L61/2092 ,  H04L61/3005

    Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

    Abstract translation: 公开了用于允许外部控制（例如选择或重新编程）用于总线通信识别的设备标识的电子设备中的设备识别生成。 以这种方式，可以选择或重新编程耦合到系统中的公共通信总线的电子设备的设备标识，以确保它们是唯一的，以避免总线通信冲突。 在某些方面，为了在电子设备中选择或重新编程设备识别，外部源可以电耦合到电子设备。 外部源在电子设备中用设备识别生成电路闭合电路。 封闭电路提供了可由设备识别生成电路检测的期望的电特性。 设备识别生成电路被配置为根据检测到的来自外部源的闭路电气特性产生设备标识。

    Fast activation during wake up in an audio system
    28.
    发明授权
    Fast activation during wake up in an audio system 有权

    公开(公告)号：US11704086B2

    公开(公告)日：2023-07-18

    申请号：US16894096

    申请日：2020-06-05

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio ,  Sharon Graif ,  Jason Gonzalez

    IPC: G06F3/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/362

    CPC classification number: G06F3/162 ,  G06F13/3625 ,  G06F13/4072 ,  G06F13/4282

    Abstract: Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

    I2C bus architecture using shared clock and dedicated data lines
    29.
    发明授权
    I2C bus architecture using shared clock and dedicated data lines 有权

    公开(公告)号：US11520729B2

    公开(公告)日：2022-12-06

    申请号：US17307842

    申请日：2021-05-04

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Sharon Graif ,  Lior Amarilio ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F1/08 ,  G06F13/20

    Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

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