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    High Performance, High Capacity Memory Modules and Systems
    21.
    发明申请
    High Performance, High Capacity Memory Modules and Systems 审中-公开

    公开(公告)号：US20200348870A1

    公开(公告)日：2020-11-05

    申请号：US16880244

    申请日：2020-05-21

    Applicant: Rambus Inc.

    Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

    Load reduced memory module
    22.
    发明授权
    Load reduced memory module 有权

    公开(公告)号：US10813216B2

    公开(公告)日：2020-10-20

    申请号：US16657130

    申请日：2019-10-18

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan

    IPC: G11C5/06 ,  H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F1/18 ,  G11C5/04 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40

    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

    Folded memory modules
    25.
    发明授权
    Folded memory modules 有权
    折叠内存模块

    公开(公告)号：US09489323B2

    公开(公告)日：2016-11-08

    申请号：US14182986

    申请日：2014-02-18

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

    IPC: G06F13/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/4022 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694

    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

    Abstract translation: 存储器模块包括数据接口，该数据接口包括多个数据线和耦合在数据接口和到一个或多个存储器的数据路径之间的多个可配置开关。 可以通过启用或禁用可配置开关的不同子集来配置内存模块的有效宽度。 可配置开关可以由手动开关，存储器模块上的缓冲器，外部存储器控制器或存储器模块上的存储器来控制。

    MEMORY REPAIR USING EXTERNAL TAGS
    27.
    发明申请
    MEMORY REPAIR USING EXTERNAL TAGS 有权
    使用外部标签进行记忆修复

    公开(公告)号：US20150162101A1

    公开(公告)日：2015-06-11

    申请号：US14407318

    申请日：2013-10-31

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ian Shaeffer

    IPC: G11C29/44 ,  G06F11/10

    CPC classification number: G11C29/4401 ,  G06F11/1016 ,  G06F11/1072 ,  G11C29/808 ,  G11C29/846

    Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

    Abstract translation: 存储器设备（100）包括修复存储器块的额外列（114）。 这些修复存储器瓦片同时被以与主阵列的存储器瓦片相同的方式被访问。 修复列的输出代替主阵列（112）的列的输出。 取代的主阵列列由存储在外部的存储器件的标签（121）决定。 使用访问的部分地址查询外部标记。 如果访问的地址对应于外部标签中的地址，则将标签信息提供给存储设备。 标签信息确定主阵列中的哪个列由修复列的输出替代。 由于主阵列的每列在访问期间提供一位，所以修复列可以逐个单元替换主阵列单元。

    DRAM METHOD, COMPONENTS, AND SYSTEM CONFIGURATIONS FOR ERROR MANAGEMENT
    28.
    发明申请
    DRAM METHOD, COMPONENTS, AND SYSTEM CONFIGURATIONS FOR ERROR MANAGEMENT 审中-公开
    DRAM方法，组件和系统配置错误管理

    公开(公告)号：US20140351673A1

    公开(公告)日：2014-11-27

    申请号：US14285467

    申请日：2014-05-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan ,  Brent Haukness ,  Scott C. Best ,  Wayne F. Ellis

    IPC: G06F11/10

    CPC classification number: G06F11/1048 ,  G06F11/1092 ,  G06F2211/1092 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

    Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.

    Abstract translation: 公开了一种存储器件，其包括用于存储数据字的存储位置行和备用行元件。 数据字通过用于产生用于校正X位错误的错误信息的错误代码进行编码，或者检测Y位错误，其中Y大于X.备用行元件具有替代的存储位置。 逻辑响应于检测到的错误，以（1）能够基于错误信息来校正数据字，其中存在不超过X位错误，以及（2）将备用行元素替换为存在行的一部分 数据字中至少有Y位错误。

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