公开(公告)号：US09570610B2

公开(公告)日：2017-02-14

申请号：US15093048

申请日：2016-04-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/423 ,  H01L27/115 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US09543315B1

公开(公告)日：2017-01-10

申请号：US15212331

申请日：2016-07-18

Applicant: Renesas Electronics Corporation

Inventor： Hiraku Chakihara ,  Satoshi Abe

IPC: H01L29/78 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L27/11573 ,  H01L27/0629 ,  H01L28/90 ,  H01L29/66181 ,  H01L29/7833

Abstract: The memory cell includes a gate insulating film, a control gate electrode, a cap insulating film, a cap layer, another gate insulating film, and a memory gate electrode. A laminated capacitive element includes a capacitive electrode which is constituted by a sub-electrode and another sub-electrode formed of mesa portions (protruding portions) disposed on the sub-electrode at a predetermined interval and each having an upper surface and side surfaces, a capacitive insulating film which is formed along an upper surface of the sub-electrode and the upper surface and the side surfaces of the another sub-electrode, and another capacitive electrode which is formed on the capacitive insulating film. Further, the control gate electrode and the sub-electrode are made of a conductor film, the cap layer and the another sub-electrode are made of other conductor film, and the memory gate electrode and the another capacitive electrode are made of another conductor film.

Abstract translation: 存储单元包括栅极绝缘膜，控制栅电极，帽绝缘膜，盖层，另一栅极绝缘膜和存储栅电极。 叠层电容元件包括由副电极构成的电容电极和以预定间隔设置在副电极上的台面部（突出部）形成的各自具有上表面和侧面的另一副电极， 沿着副电极的上表面和另一子电极的上表面和侧表面形成的电容绝缘膜和形成在电容绝缘膜上的另一电容电极。 此外，控制栅电极和副电极由导体膜制成，盖层和另一副电极由其他导体膜制成，并且存储栅电极和另一电容电极由另一导体膜 。

公开(公告)号：US20160260795A1

公开(公告)日：2016-09-08

申请号：US14992067

申请日：2016-01-11

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Abe ,  Hiraku Chakihara ,  Kyoko Umeda ,  Yoshiyuki Kawashima ,  Kentaro Saito

IPC: H01L49/02 ,  H01L27/115

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/11573

Abstract: In a semiconductor device including a nonvolatile memory, a novel stacked capacitive element is provided. The semiconductor device includes the stacked capacitive element including a first capacitive electrode made of an n-type well region formed in a semiconductor substrate, a second capacitive electrode formed so as to overlap the first capacitive electrode via a first capacitive insulating film, a third capacitive electrode formed so as to overlap the second capacitive electrode via a second capacitive insulating film, and a fourth capacitive electrode formed so as to overlap the third capacitive electrode via a third capacitive insulating film. To the first and third capacitive electrodes, a first potential is applied and, to the second and fourth capacitive electrodes, a second potential different from the first potential is applied.

Abstract translation: 在包括非易失性存储器的半导体器件中，提供了一种新颖的叠层电容元件。 半导体器件包括堆叠的电容元件，其包括由形成在半导体衬底中的n型阱区域构成的第一电容电极，经由第一电容绝缘膜形成为与第一电容电极重叠的第二电容电极，第三电容 电极，其经由第二电容绝缘膜与第二电容电极重叠形成，第四电容电极通过第三电容绝缘膜与第三电容电极重叠形成。 对于第一和第三电容电极，施加第一电位，并且向第二和第四电容电极施加不同于第一电位的第二电位。

公开(公告)号：US20160064402A1

公开(公告)日：2016-03-03

申请号：US14829638

申请日：2015-08-19

Applicant: Renesas Electronics Corporation

Inventor： Kyoko Umeda ,  Yoshiyuki Kawashima ,  Hiraku Chakihara

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/02 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L21/32135 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42344 ,  H01L29/66833

Abstract: In method for manufacturing a semiconductor device including a nonvolatile memory, a new method for manufacturing a capacitor element is provided. After working a control gate electrode, a gate insulation film including an electric charge accumulation section, and a memory gate electrode of a memory cell, in order to protect the memory cell, a p-type well of a MISFET is formed in a state the control gate electrode, the gate insulation film, and the memory gate electrode are covered by an insulation film. Also, this insulation film is used as a capacitor insulation film of a laminated type capacitor element.

Abstract translation: 在制造包括非易失性存储器的半导体器件的方法中，提供了一种用于制造电容器元件的新方法。 为了保护存储单元，在加工了控制栅电极，包括电荷累积部分的栅极绝缘膜和存储单元的存储栅极之后，形成MISFET的p型阱，状态为 控制栅电极，栅极绝缘膜和存储栅电极被绝缘膜覆盖。 此外，该绝缘膜用作叠层型电容器元件的电容器绝缘膜。

公开(公告)号：US20160064226A1

公开(公告)日：2016-03-03

申请号：US14829614

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Akio Nishida

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L21/31053 ,  H01L21/0217 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7847

Abstract: Improvements are achieved in the properties of a semiconductor device including a MISFET and a nonvolatile memory. Over a gate electrode included in the MISFET and a control gate electrode and a memory gate electrode each included in a memory cell, a stress application film is formed of a silicon nitride film. Then, by removing the silicon nitride film from over the control gate electrode and the memory gate electrode, an opening is formed over the control gate electrode and the memory gate electrode. Then, in a state where the opening is formed in the silicon nitride film, heat treatment is performed to apply a stress to the MISFET. By thus removing the stress application film (silicon nitride film) from over the memory cell, it is possible to avoid the degradation of the properties of the memory cell due to H (hydrogen) in the silicon nitride film.

Abstract translation: 在包括MISFET和非易失性存储器的半导体器件的性能方面实现了改进。 在包括在MISFET中的栅电极和每个包括在存储单元中的控制栅电极和存储栅电极中，应力施加膜由氮化硅膜形成。 然后，通过从控制栅电极和存储栅电极上除去氮化硅膜，在控制栅电极和存储栅极上形成一个开口。 然后，在氮化硅膜中形成开口的状态下，进行热处理，向MISFET施加应力。 通过从存储单元上除去应力施加膜（氮化硅膜），可以避免由于氮化硅膜中的H（氢）导致的存储单元的性质的劣化。

公开(公告)号：US09275956B2

公开(公告)日：2016-03-01

申请号：US14739818

申请日：2015-06-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Uchiyama ,  Hiraku Chakihara ,  Teruhisa Ichise ,  Michimoto Kaminaga

IPC: H01L23/544 ,  H01L23/58 ,  G03F9/00 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/768 ,  H01L21/66 ,  H01L21/306 ,  H01L21/78 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L23/544 ,  G03F9/7076 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L27/0207 ,  H01L29/78 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate includes scribe and product regions, with grooves formed in the scribe region. The grooves are embedded with an insulating film to provide an isolation region, and an active region, including semiconductor elements, is formed in the product region. Dummy patterns are formed in the scribe region, which include a first dummy pattern and second dummy patterns for preventing dishing of the insulating film. The second dummy patterns are surrounded and defined by the isolation region. A target pattern for optical pattern recognition is arranged over the first dummy pattern, and includes a first conductive film. A plane area of the first dummy pattern is larger than a plane area of each of the second dummy patterns, and the first dummy pattern and the second dummy patterns are arranged in order from an edge of the semiconductor substrate toward the product region.

Abstract translation: 半导体衬底包括划线和产品区域，在刻划区域中形成有沟槽。 凹槽嵌入绝缘膜以提供隔离区域，并且在产品区域中形成包括半导体元件的有源区域。 在划线区域中形成有虚拟图案，其包括第一虚设图案和用于防止绝缘膜凹陷的第二虚设图案。 第二虚拟图案由隔离区域包围和限定。 用于光学图案识别的目标图案被布置在第一虚设图案之上，并且包括第一导电膜。 第一虚设图形的平面区域大于第二虚设图案的平面面积，第一虚设图案和第二虚设图案从半导体衬底的边缘朝向产品区域的顺序排列。

公开(公告)号：US09263291B2

公开(公告)日：2016-02-16

申请号：US14079120

申请日：2013-11-13

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

IPC: H01L21/44 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20160027651A1

公开(公告)日：2016-01-28

申请号：US14801798

申请日：2015-07-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Kentaro Saito ,  Hiraku Chakihara

IPC: H01L21/28 ,  H01L29/40 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

Abstract: The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are formed over the side surface of a control gate electrode formed in a memory cell region, the surface of a cap insulating film formed in the memory cell region, and the surface of the part, which remains in a peripheral circuit region, of an insulating film. The step of forming the sacrificial oxide films includes the steps of: oxidizing the side surface of the control gate electrode by a thermal oxidation method; and oxidizing the surface of the cap insulating film and the surface of the part, which remains in the peripheral circuit region, of the insulating film by an ISSG oxidation method.

Abstract translation: 本发明改进了半导体器件的性能。 在半导体器件的制造方法中，在形成在存储单元区域中的控制栅电极的侧表面上形成牺牲氧化物膜，形成在存储单元区域中的帽绝缘膜的表面和部件的表面 ，其保留在绝缘膜的外围电路区域中。 形成牺牲氧化膜的步骤包括以下步骤：通过热氧化法氧化控制栅电极的侧表面; 并通过ISSG氧化法氧化绝缘膜上的帽绝缘膜的表面和保留在外围电路区域中的部分的表面。

公开(公告)号：US09214350B2

公开(公告)日：2015-12-15

申请号：US14283243

申请日：2014-05-21

Applicant: Renesas Electronics Corporation

Inventor： Yasushi Ishii ,  Hiraku Chakihara

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L23/5223 ,  H01L21/28273 ,  H01L21/76805 ,  H01L21/76895 ,  H01L27/11521 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7885 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.

Abstract translation: 提高了半导体器件的性能。 半导体器件具有在半导体衬底上彼此分开形成的第一电极和虚拟电极，形成在第一电极和虚拟电极之间的第二电极，在第一电极的周向侧表面处，并且在周向侧表面 以及形成在第一电极和第二电极之间的电容绝缘膜。 第一电极，第二电极和电容绝缘膜形成电容元件。 此外，半导体器件具有穿过层间绝缘膜并与第一电极电耦合的第一插塞和穿过层间绝缘膜的第二插塞，并且与形成在侧表面处的第二电极的部分电连接 与第一电极侧相对的虚拟电极。

公开(公告)号：US09099334B2

公开(公告)日：2015-08-04

申请号：US14089959

申请日：2013-11-26

Applicant: Renesas Electronics Corporation

Inventor： Yasushi Ishii ,  Hiraku Chakihara ,  Kentaro Saito

IPC: H01L21/3205 ,  H01L27/088 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract translation: 在包括在相同基板上具有不同特性的多个场效应晶体管的半导体器件的制造成品率方面的改进。 通过将各向异性干法蚀刻与各向同性湿蚀刻或各向同性干法蚀刻相结合，形成具有不同侧壁长度的三种类型的侧壁。 通过减少各向异性干蚀刻步骤的数量，在布置密度高的第三n型MISFET区域和第三p型MISFET区域中，可以防止半导体衬底在n型栅极之间被部分切割 彼此相邻的n型栅电极和彼此相邻的p型栅极之间，以及彼此相邻的p型栅电极。