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公开(公告)号:US20210174862A1
公开(公告)日:2021-06-10
申请号:US17100850
申请日:2020-11-21
Applicant: Rambus Inc.
Inventor: Frederick A. Ware , James E. Harris
IPC: G11C11/4093 , G11C5/04 , G11C5/06 , G11C8/12 , G11C7/22
Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
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公开(公告)号:US10811062B2
公开(公告)日:2020-10-20
申请号:US16528523
申请日:2019-07-31
Applicant: Rambus Inc.
Inventor: James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC: G11C7/00 , G11C7/10 , G11C7/08 , G11C5/02 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/06 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/10
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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公开(公告)号:US20200152258A1
公开(公告)日:2020-05-14
申请号:US16693071
申请日:2019-11-22
Applicant: Rambus Inc.
Inventor: Frederick A. Ware , James E. Harris
IPC: G11C11/4093 , G11C7/22 , G11C8/12 , G11C5/06 , G11C5/04
Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
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公开(公告)号:US10652493B2
公开(公告)日:2020-05-12
申请号:US16197270
申请日:2018-11-20
Applicant: Rambus Inc.
Inventor: John Ladd , Michael Guidash , Craig M. Smith , Thomas Vogelsang , Jay Endsley , Michael T. Ching , James E. Harris
Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.
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公开(公告)号:US10594973B2
公开(公告)日:2020-03-17
申请号:US15497093
申请日:2017-04-25
Applicant: Rambus Inc.
Inventor: Thomas Vogelsang , Michael Guidash , Song Xue , James E. Harris
Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.
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公开(公告)号:US10165209B2
公开(公告)日:2018-12-25
申请号:US15328207
申请日:2015-07-23
Applicant: Rambus Inc.
Inventor: John Ladd , Michael Guidash , Craig M. Smith , Thomas Vogelsang , Jay Endsley , Michael T. Ching , James E. Harris
Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.
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公开(公告)号:US10136090B2
公开(公告)日:2018-11-20
申请号:US14772311
申请日:2014-03-14
Applicant: Rambus Inc.
Inventor: Thomas Vogelsang , Michael Guidash , Song Xue , Maxim Smirnov , Craig M. Smith , Jay Endsley , James E. Harris
IPC: H04N5/225 , H04N5/3745 , H01L27/146 , H04N5/347 , H04N5/376
Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.
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公开(公告)号:US10104318B2
公开(公告)日:2018-10-16
申请号:US15100976
申请日:2014-12-03
Applicant: Rambus Inc.
Inventor: Craig M. Smith , Frank Armstrong , Jay Endsley , Thomas Vogelsang , James E. Harris , John Ladd , Michael Guidash
Abstract: A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.
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公开(公告)号:US20170337965A1
公开(公告)日:2017-11-23
申请号:US15522182
申请日:2015-11-04
Applicant: Rambus Inc.
Inventor: Frederick A. Ware , James E. Harris
IPC: G11C11/4093 , G11C5/06 , G11C8/12 , G11C5/04
CPC classification number: G11C11/4093 , G11C5/04 , G11C5/063 , G11C7/22 , G11C8/12
Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
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公开(公告)号:US09570126B2
公开(公告)日:2017-02-14
申请号:US15138424
申请日:2016-04-26
Applicant: Rambus Inc.
Inventor: James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC: G11C7/00 , G11C7/12 , G11C5/02 , G11C7/10 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/06 , G11C7/08 , G11C7/22
CPC classification number: G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
Abstract translation: 存储器组件内的行激活操作相对于子行执行,而不是完整的存储行,以减少功耗。 此外,代替激活响应于行命令的子代码,延迟激活操作被延迟,直到接收到指定要执行的列操作的列命令和被激活的子代。
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