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73 条记录 (耗时 0.046 秒)

    Remapping memory devices during operation
    25.
    发明授权
    Remapping memory devices during operation 有权
    操作期间重映射存储器件

    公开(公告)号：US06816986B1

    公开(公告)日：2004-11-09

    申请号：US09473483

    申请日：1999-12-28

    申请人： Blaise Fanning

    发明人： Blaise Fanning

    IPC分类号： H02H305

    CPC分类号： G06F11/1666 ,  G06F11/1658 ,  G06F11/20 ,  G11C29/76

    摘要： According to the invention, systems, apparatus and methods are disclosed for automatically replacing semiconductor based memory in a system while that system is operating. Replacement is accomplished by blocking access to the memory devices to be swapped, copying the contents of the faulty device to the replacement device, swapping the IDs of the two devices, and re-enabling access to the replaced device. This replacement is triggered by interrupts from the error detection logic. After replacement, the system automatically checks the faulty device to determine its suitability for use as a spare in the future. The determination is made by repeatedly writing and reading a pseudo-random pattern into the device and logging any errors.

    摘要翻译： 根据本发明，公开了系统，装置和方法，用于在系统运行时自动替换系统中的半导体存储器。 替换是通过阻止访问要交换的存储设备，将故障设备的内容复制到替换设备，交换两个设备的ID，以及重新启用对更换的设备的访问来实现的。 该更换由错误检测逻辑的中断触发。 更换后，系统会自动检查故障设备，以确定其将来适合作为备用设备使用。 通过重复写入和读取伪随机模式到设备中并记录任何错误来进行确定。

    Translation of virtual addresses in a computer graphics system
    26.
    发明授权
    Translation of virtual addresses in a computer graphics system 失效
    在计算机图形系统中翻译虚拟地址

    公开(公告)号：US5313577A

    公开(公告)日：1994-05-17

    申请号：US748357

    申请日：1991-08-21

    申请人： Kim Meinerth ,  Colyn Case ,  Chris Franklin ,  Blaise Fanning ,  Rodney Gamache

    发明人： Kim Meinerth ,  Colyn Case ,  Chris Franklin ,  Blaise Fanning ,  Rodney Gamache

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G09G5/06 ,  G09G5/08 ,  G09G5/39 ,  G06F15/00

    CPC分类号： G09G5/39 ,  G06F12/1027 ,  G06F9/3879 ,  G09G5/06 ,  G09G5/08 ,  G06F12/0831 ,  G09G2360/121 ,  G09G2360/127

    摘要： A computer graphics processor capable of reading from, and writing to, virtual memory. The invention provides a graphics processing unit which includes, among other things, an graphic processor in the form of an address generator which retrieves data from memory locations, and writes data to memory locations. The address generator retrieves data from memory locations memory access request directly to a memory control unit, which retrieves the contents of the memory location. Prior to issuing the request, the address generator sends the address to a virtual translation unit, which translates the virtual address to a physical address. The virtual translation/FIFO control unit also contains three translation buffers, in which are stored the most recently accessed virtual addresses, which, in many situations, enables the virtual translation/FIFO control unit to translate the virtual address using less memory accesses.

    摘要翻译： 能够读取和写入虚拟内存的计算机图形处理器。 本发明提供了一种图形处理单元，其中包括地址发生器形式的图形处理器，其从存储器位置检索数据，并将数据写入存储单元。 地址生成器将存储器存储器访问请求中的数据直接检索到存储器控制单元，存储器控制单元检索存储器位置的内容。 在发出请求之前，地址生成器将地址发送到虚拟转换单元，该虚拟转换单元将虚拟地址转换为物理地址。 虚拟转换/ FIFO控制单元还包含三个转换缓冲器，其中存储最近访问的虚拟地址，在许多情况下，虚拟转换/ FIFO控制单元能够使用较少的存储器访问来转换虚拟地址。

    MEMORY LATENCY MANAGEMENT
    28.
    发明申请
    MEMORY LATENCY MANAGEMENT 有权
    内存管理

    公开(公告)号：US20160034345A1

    公开(公告)日：2016-02-04

    申请号：US14775848

    申请日：2014-02-26

    申请人： Robert J. ROYER, JR. ,  Blaise FANNING ,  Eng Hun OOI ,  INTEL CORPORATION

    发明人： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

    IPC分类号： G06F11/10 ,  G06F12/08

    CPC分类号： G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

    摘要： Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

    摘要翻译： 描述了用于管理存储器延迟操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控​​制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，以及实现数据管理策略 响应于纠错码指示器。 还公开并要求保护其他实施例。

    ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM
    30.
    发明申请
    ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM 有权
    在多级存储器系统中的异步代理数据引导

    公开(公告)号：US20150169439A1

    公开(公告)日：2015-06-18

    申请号：US14133097

    申请日：2013-12-18

    申请人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

    发明人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

    IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/126

    摘要： A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

    摘要翻译： 处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。 此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。