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    Variable delay circuit
    21.
    发明授权
    Variable delay circuit 失效
    可变延迟电路

    公开(公告)号：US06169436A

    公开(公告)日：2001-01-02

    申请号：US09146602

    申请日：1998-09-03

    Applicant: Roland Marbot

    Inventor： Roland Marbot

    IPC: H03H1126

    CPC classification number: H03K5/133

    Abstract: A delay circuit includes a primary circuit receiving an input signal and outputting two intermediate signals having a delay therebetween. A combination circuit with two modules that output a combination signal on the basis of the addition with weighting and effect of integration of the intermediate signals and of their conjugate. Each module includes a discharging circuit and a charging circuit, which each have switching elements controlling the connection between a common line and first and second supply potentials. These connections use a variable resistor and a non-variable resistor so as to ensure the permanent participation of the two modules in the charging or discharging of a capacitor. This delay circuit is particularly useful in CMOS circuits.

    Abstract translation: 延迟电路包括接收输入信号的一次电路，并且输出两者之间具有延迟的两个中间信号。 具有两个模块的组合电路，其基于加权和基于中间信号和它们的共轭的积分的影响而输出组合信号。 每个模块包括放电电路和充电电路，每个充电电路各自具有控制公共线与第一和第二电源电位之间的连接的开关元件。 这些连接使用可变电阻器和不可变电阻器，以确保两个模块在电容器的充电或放电中的永久性参与。 该延迟电路在CMOS电路中特别有用。

    Phase-locked loop and resulting frequency multiplier
    22.
    发明授权
    Phase-locked loop and resulting frequency multiplier 有权
    锁相环和产生的倍频器

    公开(公告)号：US6150855A

    公开(公告)日：2000-11-21

    申请号：US192440

    申请日：1998-11-16

    Applicant: Roland Marbot

    Inventor： Roland Marbot

    IPC: H03B19/14 ,  H03K5/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/16

    CPC classification number: H03L7/0814 ,  H03B19/14 ,  H03K5/00006 ,  H03L7/089 ,  H03L7/16

    Abstract: The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

    Abstract translation: 倍频器20由包括相位比较器11的锁相环实现，该相位比较器11用于指令多个延迟元件130至137，延迟元件130至137将连续的相移信号CL0-CL7提供给由“独占或”门构成的逻辑加法器16。

    Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate
    23.
    发明授权
    Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate 有权
    具有四个二乘互补输入和两个互补输出的独占逻辑门，以及并入所述门的倍频器

    公开(公告)号：US6137309A

    公开(公告)日：2000-10-24

    申请号：US159316

    申请日：1998-09-23

    Applicant: Pascal Couteaux ,  Roland Marbot

    Inventor： Pascal Couteaux ,  Roland Marbot

    IPC: H03K5/00 ,  H03K19/21

    CPC classification number: H03K19/215 ,  H03K5/00006

    Abstract: An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

    Abstract translation: 具有四个二乘互补输入和两个互补输出的异或逻辑门。 据说这种异或门的结构是对称的，因为门的传播时间是相同的，两对互补输入中的任何一个都被切换，无论输出的转换的性质如何， 该对输入不切换。 所公开的装置能够通过消除某些节点的浮动特性来进一步减少通过门传播信号边缘所花费的时间差异。 它还涉及包括诸如此类的异或门树的倍频器。

    Frequency multiplier using XOR/NXOR gates which have equal propagation delays
    25.
    发明授权
    Frequency multiplier using XOR/NXOR gates which have equal propagation delays 失效
    使用具有相等传播延迟的XOR / NXOR门的倍频器

    公开(公告)号：US5614841A

    公开(公告)日：1997-03-25

    申请号：US362892

    申请日：1994-12-23

    Applicant: Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

    Inventor： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

    IPC: H01L21/8234 ,  H01L27/088 ,  H03K5/00 ,  H03K19/21

    CPC classification number: H03K19/215 ,  H03K5/00006

    Abstract: The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.

    Abstract translation: 具有两个输入（A，B）的异或类型的门（11）以树形结构设置在从接收树的输入信号的输入层开始的集成电路的连续层中。 每个栅极的输出端连接到相邻层中的栅极的输入端。 每个门包括两个单元（11a，11b），其响应于来自两个输入中的一个的两个相应的互补信号（A，NA; B，NB）而基本同时地切换，并提供表示互补功能的各个输出信号 XOR，NXOR）的OR类型。 这使得可以获得完全相等的传播时间，无论树的活动输入或要传播的边缘的传播时间完全相等，无论树的活动输入或要传播的边缘可以是什么。

    Adjustable delay circuit of the current intensity having delay as a hyperbolic function
    26.
    发明授权
    Adjustable delay circuit of the current intensity having delay as a hyperbolic function 失效
    具有作为双曲线函数的延迟的电流强度的可调延迟电路

    公开(公告)号：US5463343A

    公开(公告)日：1995-10-31

    申请号：US809181

    申请日：1991-12-18

    Applicant: Roland Marbot

    Inventor： Roland Marbot

    IPC: H03K5/13 ,  H03H11/26 ,  H03K5/14 ,  H03H17/28 ,  H03H17/296

    CPC classification number: H03H11/265

    Abstract: The delay device 10 includes an ECL gate 11, the current source 16 and two resistive load elements 14, 15 of which are associated with an adjusting circuit 23 producing an adjusting voltage Vd, to cause the polarization current of the current source to vary hyperbolically, and a voltage Vh for keeping constant the voltage at the collectors of the transistors 12 and 13 of the gate 11. The delay device 10 causes the delays between the input signals IN, IN* and output signals OUT, OUT* to vary linearly. The invention is applicable in particular to systems for the transmission of digital data at a very high rate, of more than 1 gigabit per second, for example.

    Abstract translation: 延迟装置10包括ECL门11，电流源16和两个电阻负载元件14,15与调节电路23相关联，调节电路23产生调节电压Vd，以使电流源的极化电流双曲变化， 以及用于保持栅极11的晶体管12和13的集电极处的电压恒定的电压Vh。延迟装置10使得输入信号IN，IN *和输出信号OUT，OUT *之间的延迟线性变化。 本发明特别适用于例如以超过1吉比特/秒的速率以非常高的速率传输数字数据的系统。

    Transceiver for bidirectional link, integrated circuit including the transceiver, and application to communication between units of a system
    28.
    发明授权
    Transceiver for bidirectional link, integrated circuit including the transceiver, and application to communication between units of a system 失效
    收发器用于双向链路，集成电路包括收发器，以及应用于系统单元之间的通信

    公开(公告)号：US5347538A

    公开(公告)日：1994-09-13

    申请号：US843210

    申请日：1992-02-28

    Applicant: Roland Marbot

    Inventor： Roland Marbot

    IPC: H03K5/02 ,  H04B1/58 ,  H04L5/14 ,  H04L29/00 ,  H04L29/12 ,  H04B1/38 ,  H04L5/16

    CPC classification number: H04B1/58 ,  H03K5/026 ,  H04L5/1423

    Abstract: Transceiver for transmission over serial bi-directional links having a bi-directional amplifier including an impedance (R) for adaptation to the line and connected to it, a generator (G1) commanded for transmission and supplying the adaptation impedance (R) and the line in parallel, detection device (G2, r) for furnishing a measurement signal (V) representative of either the current circulating in the adaptation impedance (R) when the generator (G1) is active, or the sum of the current in the adaptation impedance (R) and a compensation value when the first generator (G1) is not active. The compensation value is determined so as to make the measurement signal (V) independent of the transmission state of the transceiver.

    Abstract translation: 用于通过串行双向链路传输的收发器，具有双向放大器，该双向放大器包括用于适应线路并连接到其上的阻抗（R），命令用于传输和提供自适应阻抗（R）的线路 用于提供表示当发电机（G1）有效时在自适应阻抗（R）中循环的电流的测量信号（V）或适应阻抗中的电流之和的检测装置（G2，r） （R）和第一发生器（G1）不起作用时的补偿值。 确定补偿值，使得测量信号（V）独立于收发器的传输状态。

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