公开(公告)号：US07580496B2

公开(公告)日：2009-08-25

申请号：US10832803

申请日：2004-04-26

Applicant: Roland Marbot ,  Franck Hellard

Inventor： Roland Marbot ,  Franck Hellard

IPC: H03D3/24

CPC classification number: H04L7/0337 ,  H03K5/133 ,  H03L7/091 ,  H04L7/0037

Abstract: A circuit for receiving digital data arriving in series comprising a circuit for generating a reference dock and a circuit for oversampling the received data memorizing the samples sampled at the rate of several clocks phase-shifted with respect to the reference clock, the oversampling circuit comprising means for selecting and providing as output data samples representative of the received data and, further, a detection circuit identifying the variations of the phase shift between the reference clock edges and the transitions of the received data by analyzing the memorized samples, the detection circuit controlling a frequency variation of the reference dock when the phase shift variations repeat over several sampling cycles.

Abstract translation: 一种用于接收数字数据串行电路的电路，包括用于产生参考基准的电路和用于对存储相对于参考时钟相移的几个时钟采样的采样采样的接收数据进行过采样的电路，该过采样电路包括： 用于选择和提供表示所接收数据的输出数据样本，以及另外，检测电路通过分析存储的样本来识别参考时钟边沿与接收数据的转变之间的相移的变化，检测电路控制 当相移变化在几个采样周期内重复时，参考基准的频率变化。

公开(公告)号：US5596285A

公开(公告)日：1997-01-21

申请号：US293190

申请日：1994-08-19

Applicant: Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

Inventor： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

IPC: H03K19/0175 ,  H03H11/30 ,  H03K19/00 ,  H04L25/08 ,  H03K17/16

CPC classification number: H03H11/30 ,  H03K19/0005 ,  H04L25/08

Abstract: An integrated circuit (IC) includes a device (10) that adapts the impedance to the characteristic impedance (Zc) of transmission lines (13) each connecting a transmitter (11) to a receiver (12). Two adaptation blocks (14, 15) reproduce the respective structures of the transmitters (11) and receivers (12) and their impedance is adapted by a reference resistor (Rr). A closed loop control device (Len, Lep, Lrn, Lrp) reproduces the adaptation conditions in the transmitters (11) and receivers (12) respectively.

Abstract translation: 集成电路（IC）包括将阻抗适配到每个将发送器（11）连接到接收器（12）的传输线（13）的特性阻抗（Zc）的装置（10）。 两个适配块（14,15）再现发射器（11）和接收器（12）的相应结构，并且它们的阻抗由参考电阻器（Rr）适配。 闭环控制装置（Len，Lep，Lrn，Lrp）分别再现发射机（11）和接收机（12）中的适应条件。

公开(公告)号：US5268937A

公开(公告)日：1993-12-07

申请号：US727430

申请日：1991-07-09

Applicant: Roland Marbot

Inventor： Roland Marbot

IPC: H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L25/40 ,  H04L23/00

CPC classification number: H04L7/0337 ,  H04L7/048

Abstract: The digital data transmission is of the type including the addition of clock and synchronizing information to the data to constitute the transmission signal, and the determination of the transmission speed from this received information. According to the invention, this information, in the transmission signal, comprises a synchronizing edge (SYNC) added to each group of N data bits (D0-D7, OP), and the determination of the transmission speed comprises producing N clock signals (CL0-CL9) from identical successive delays (480-489) of a synchronizing edge detected.

Abstract translation: 数字数据传输是包括添加时钟和同步信息到数据以构成发送信号的类型，以及从该接收到的信息确定传输速度。 根据本发明，在发送信号中，该信息包括添加到每组N个数据比特（D0-D7，OP）的同步边缘（SYNC），并且传输速度的确定包括产生N个时钟信号（CL0 -CL9）从检测到的同步边缘的相同连续延迟（480-489）。

公开(公告)号：US4675651A

公开(公告)日：1987-06-23

申请号：US724879

申请日：1985-04-19

Applicant: Roland Marbot ,  Jean-Pierre Polonovski

Inventor： Roland Marbot ,  Jean-Pierre Polonovski

IPC: H03M1/44 ,  H03M1/00

CPC classification number: H03M1/366

Abstract: A dichotomizing, high speed analog - digital comprises an input stage for the voltage - current conversion of the analog signal, a reference current source, a sequence of N-1 identical cells in series, each comprising a comparator and current dividers, a terminal cell incorporating a comparator, a digital coder receiving a digital signal from each cell and, optionally, a link positioned between the consecutive cells. The analog signal is processed in the cells entirely in current form, the link means making it possible to isolate the potentials between successive cells.

Abstract translation: 二分法，高速模拟数字包​​括用于模拟信号的电压 - 电流转换的输入级，参考电流源，串联的N-1个相同单元的序列，每个包括比较器和电流分配器，终端单元 结合了比较器，数字编码器从每个单元接收数字信号，以及可选地，位于连续小区之间的链路。 模拟信号在电池中完全以当前形式进行处理，该连接装置使得可以隔离连续电池之间的电位。

公开(公告)号：US07607044B2

公开(公告)日：2009-10-20

申请号：US11509304

申请日：2006-08-23

Applicant: Gerard Humeau ,  Roland Marbot

Inventor： Gerard Humeau ,  Roland Marbot

IPC: G06F11/00

CPC classification number: G06F11/3636

Abstract: A method for monitoring the execution of a program by a processor of an electronic circuit comprises operations of collecting monitoring data within the circuit and of transmitting the monitoring data to a device for debugging the program. The monitoring data are transmitted via a connection external to the circuit, comprising at least one serial connection. The monitoring data are serialized within the circuit before being transmitted, then restored within the device for tuning the program.

Abstract translation: 一种用于监视由电子电路的处理器执行程序的方法包括收集电路内的监视数据并将监视数据发送到用于调试程序的设备的操作。 监视数据经由电路外部的连接发送，包括至少一个串行连接。 监控数据在发送之前在电路内串行化，然后在设备内恢复以调谐程序。

公开(公告)号：US06208182B1

公开(公告)日：2001-03-27

申请号：US09184224

申请日：1998-11-02

Applicant: Roland Marbot ,  Guillaume Couzon

Inventor： Roland Marbot ,  Guillaume Couzon

IPC: H03L706

CPC classification number: H03K3/0315 ,  H03L7/091 ,  H03L7/0995

Abstract: The present invention relates to a phase-locked loop circuit including: a programmable ring oscillator generating drive signals, an assembly of latches receiving an input signal of the circuit, the latches being driven by the drive signals and generating samples by sampling of the input signal, and a logic decoding circuit receiving samples generated by latches and accordingly driving the oscillator.

Abstract translation: 本发明涉及一种锁相环电路，包括：产生驱动信号的可编程环形振荡器，接收电路输入信号的锁存器的组合，锁存器由驱动信号驱动，并通过对输入信号进行采样产生采样 以及逻辑解码电路，其接收由锁存器产生的采样并相应地驱动振荡器。

公开(公告)号：US5848109A

公开(公告)日：1998-12-08

申请号：US510458

申请日：1995-08-02

Applicant: Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

Inventor： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

IPC: H04L7/00 ,  H04L7/033 ,  H03B3/04

CPC classification number: H04L7/0337 ,  H04L7/0029

Abstract: A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si), wherein the phasing is carried out in reference to the sampling instants. The phasing includes determining phasing test instants (Pi) which refer to the sampling instants (Si) to verify whether transitions of the digital signal are leading or lagging in phase relative to the phasing test instants. The determination of the phasing test instants is achieved by adding to each sampling instant (Si) a delay Y=kR/2, in which k is a positive whole odd number other than zero and R designates a pulse repetition period of the bits of the digital signal (D). The invention has particular utility in data processing and remote data processing systems, and to telecommunication systems.

Abstract translation: 一种用于对串行数字信号（D）进行采样的处理和装置，其包括用时钟信号（C）对数字信号进行定相并在延迟时刻（Si）对数字信号进行采样，其中定相参照 抽样时刻。 定相包括确定参考采样时刻（Si）的相位测试时刻（Pi），以验证数字信号的转换是相对于定相测试时刻是在前进还是相位滞后。 定相测试时刻的确定是通过将​​延迟Y = kR / 2加到每个采样时刻（Si）来实现的，其中k是除零之外的正整数奇数，R表示 数字信号（D）。 本发明在数据处理和远程数据处理系统以及电信系统中具有特别的用途。

公开(公告)号：US5521540A

公开(公告)日：1996-05-28

申请号：US451717

申请日：1995-05-26

Applicant: Roland Marbot

Inventor： Roland Marbot

IPC: H03K5/00 ,  H03K5/13 ,  H03K19/003 ,  H03H11/26

CPC classification number: H03K19/00361 ,  H03K5/131 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00195

Abstract: A method and apparatus for multi-range delay control is disclosed. A method furnishes an output signal (S.sub.K) with a delay that is variable with respect to an input signal (e.sub.0). To enable precise adjustment as a function of a set-point delay (CN) over a plurality of scales, a succession of signals (e.sub.1, e.sub.2, . . . , e.sub.n) delayed with respect to the input signal (e.sub.0) are produced, the delay between a delayed signal (e.sub.2) and the preceding signal (e.sub.1) having a predetermined value. One of the delayed signals (e.sub.2) and a preceding signal (e.sub.1) as selected and a superposition is performed with weighting and an integral effect of the selected signals (e.sub.1, e.sub.2), the selection and weighting being determined as a function of the set-point delay (CN).

Abstract translation: 公开了一种用于多范围延迟控制的方法和装置。 一种方法为输出信号（SK）提供相对于输入信号（e0）可变的延迟。 为了能够在多个刻度上作为设定点延迟（CN）的函数进行精确调整，产生相对于输入信号（e0）延迟的一系列信号（e1，e2，...，en） 延迟信号（e2）与前一信号（e1）之间的延迟具有预定值。 经选择的信号（e1，e2）的加权和积分效应执行选择的延迟信号（e2）和前一信号（e1）之一以及叠加，所述选择和加权被确定为集合的函数 点延迟（CN）。

公开(公告)号：US5334891A

公开(公告)日：1994-08-02

申请号：US52279

申请日：1993-04-26

Applicant: Roland Marbot

Inventor： Roland Marbot

IPC: H03K5/13 ,  H03H11/26 ,  H03K5/14 ,  H03K5/159

CPC classification number: H03H11/265

Abstract: The variable delay device 10 includes an ECL gate 11 associated with an adjusting circuit 23 acting on the resistance of resistive load elements 14, 15 of transistors 12, 13 and the resistive load element 18 of the current source 16 at the gate 11 to cause the current produced by the source 16 to vary linearly while keeping the voltage at the collectors of the transistors 12, 13 constant. The range of variation of the resistances is selected in such a way that the delay between the input signals IN, IN* and OUT, OUT* varies substantially linearly. The invention is particularly applicable to systems for digital data transmission at a very high rate, of more than 1 gigabit per second.

Abstract translation: 可变延迟装置10包括与调节电路23相关联的ECL门11，该调节电路23作用在栅极11处的晶体管12,13的电阻负载元件14,15的电阻和电流源16的电阻负载元件18， 源极16产生的电流线性变化，同时保持晶体管12,13的集电极处的电压恒定。 选择电阻的变化范围使得输入信号IN，IN *和OUT，OUT *之间的延迟基本上线性地变化。 本发明特别适用于以非常高的速率超过1吉比特/秒的数字数据传输系统。

公开(公告)号：US06175885B1

公开(公告)日：2001-01-16

申请号：US08972002

申请日：1997-11-17

Applicant: Roland Marbot ,  Pascal Couteaux ,  Michel D'Hoe ,  Jean-Claude Le Bihan ,  Francis Mottini ,  R{acute over (e)}za Nezamzadeh ,  Anne Pierre-Duplessix

Inventor： Roland Marbot ,  Pascal Couteaux ,  Michel D'Hoe ,  Jean-Claude Le Bihan ,  Francis Mottini ,  R{acute over (e)}za Nezamzadeh ,  Anne Pierre-Duplessix

IPC: G06F1300

CPC classification number: H03K3/35625 ,  H03M9/00 ,  H04L7/0337

Abstract: Disclosed is a device for the conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal into n parallel signals. The device uses a scheme derived from that of a static memory cell as a sample-and-hold unit and amplifier. The device continues to perform well when the differential signal comprises noise in common mode.

Abstract translation: 公开了一种用于将以低幅度高频差分信号形式接收的串联信号转换为n个并行信号的装置。 该器件使用从静态存储单元导出的方案作为采样保持单元和放大器。 当差分信号包含共模噪声时，器件继续执行良好。