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    High performance transaction-based memory systems
    21.
    发明授权
    High performance transaction-based memory systems 有权

    公开(公告)号：US09904635B2

    公开(公告)日：2018-02-27

    申请号：US14959773

    申请日：2015-12-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mu-Tien Chang ,  Hongzhong Zheng ,  Liang Yin

    IPC: G06F13/14 ,  G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1668 ,  G06F13/4068

    Abstract: A memory system includes a master controller, an interface with a host computer, and a link bus configured to couple with a slave controller. The master controller includes an address mapping decoder, a transaction queue, and a scheduler. The address mapping decoder is configured to decode address mapping information of a memory device coupled to the slave controller. The scheduler of the master controller is configured to reorder memory transaction requests received from the host computer in the transaction queue using the address mapping information of the memory device. The memory system employs an extended open page policy based on the pending memory transaction requests in the transaction queue of the master controller.

    Smart in-module refresh for DRAM
    25.
    发明授权
    Smart in-module refresh for DRAM 有权
    DRAM的智能模块刷新

    公开(公告)号：US09524769B2

    公开(公告)日：2016-12-20

    申请号：US14850938

    申请日：2015-09-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Krishna Malladi ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4076

    CPC classification number: G11C11/40615 ,  G11C5/04 ,  G11C5/14 ,  G11C11/40618 ,  G11C11/4076

    Abstract: A dynamic Random Access Memory (DRAM) module (105) is disclosed. The DRAM module (105) can includes a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data and a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4). The DRAM module (105) can also include a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

    Abstract translation: 公开了一种动态随机存取存储器（DRAM）模块（105）。 DRAM模块（105）可以包括用于存储数据的多个存储体（205-1,205-2,205-3,205-4）和可用于刷新多个存储数据中的一个的刷新引擎（115） 银行（205-1,205-2,205-3,205-4）。 DRAM模块（105）还可以包括智能刷新组件（305），该智能刷新组件可以通过使用每次刷新无序刷新哪个存储体来刷新刷新引擎（115）。 在刷新时，智能刷新组件（305）可以使用逻辑（415）来识别事务队列（430）中的待处理事务中的最远存储体。

    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
    28.
    发明申请
    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE 有权

    公开(公告)号：US20210294697A1

    公开(公告)日：2021-09-23

    申请号：US17319844

    申请日：2021-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DIMIN NIU ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

    IPC: G06F11/10 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

    Multi-cell structure for non-volatile resistive memory
    29.
    发明授权
    Multi-cell structure for non-volatile resistive memory 有权

    公开(公告)号：US10929026B2

    公开(公告)日：2021-02-23

    申请号：US15136872

    申请日：2016-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng

    IPC: G06F12/1009 ,  G06F12/02 ,  G06F3/06 ,  G11C13/00 ,  G11C8/06

    Abstract: A non-volatile memory comprises an array of a plurality of non-volatile memory cells, a controller coupled to the array, and an evaluator coupled to an output of the array. In a first operational mode, the controller receives a logical address and selects one non-volatile memory cell for access. In a second operational mode, and the controller receives a logical address and selects N non-volatile memory cells for access in which N is an integer greater than 1. If the logical address is for a read access, in the first operational mode the evaluator is disabled and the read-address output of the array corresponds to one selected non-volatile memory cell, and in the second operational mode the evaluator determines an read-address output corresponding to the received logical address based on a read output of the N selected non-volatile memory cells.

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