Electronic device and image sharing method of electronic device

    公开(公告)号:US12262152B2

    公开(公告)日:2025-03-25

    申请号:US18109502

    申请日:2023-02-14

    Abstract: An electronic device may include: a first communication module; a second communication module; a display; and a processor, wherein the processor may be set so that, when an indication of a first image having metadata including shared information is selected, at least one object, information about at least one shared external electronic device related to the at least one object, and the first image including a share button for image transmission are displayed on the display, and the first image is transmitted to a first shared external electronic device selected from among the at least one shared external electronic device. Various other embodiments can be provided.

    System, device, and method for memory interface including reconfigurable channel

    公开(公告)号:US12008270B2

    公开(公告)日:2024-06-11

    申请号:US17994077

    申请日:2022-11-25

    Inventor: Youngwook Kim

    CPC classification number: G06F3/0659 G06F3/0604 G06F3/0679

    Abstract: A method of communicating with a memory device through a plurality of sub-channels and a control sub-channel includes; setting a first mode or a second mode. In the first mode, writing or reading first data corresponding to a command synchronized to the control sub-channel through the plurality of sub-channels, and in the second mode, independently writing or reading second data and third data respectively corresponding to different commands synchronized to the control sub-channel through the plurality of sub-channels.

    Method and electronic device processing data

    公开(公告)号:US11418452B2

    公开(公告)日:2022-08-16

    申请号:US16657796

    申请日:2019-10-18

    Abstract: An electronic device including a communication circuit receiving data transmitted from another electronic device, a memory storing instructions, and at least one processor electrically connected to the communication circuit and the memory and including a control core and a plurality of operation cores. The at least one processor may execute the stored instructions to cause the control core to receive the data from the communication circuit, to classify the received data into data flows of a specified number depending on an attribute of the data, and to respectively allocate the data flows to the plurality of operation cores.

    Storage device for supporting multiple hosts and operation method thereof

    公开(公告)号:US11409469B2

    公开(公告)日:2022-08-09

    申请号:US17129185

    申请日:2020-12-21

    Abstract: An operation method of a storage device including first and second physical functions respectively corresponding to first and second hosts includes receiving performance information from each of the first and second hosts, setting a first weight value corresponding to the first physical function and a second weight value corresponding to the second physical function, based on the received performance information, selecting one of a first submission queue, a second submission queue, a third submission queue, and a fourth submission queue based on an aggregated value table, the first and second submission queues being managed by the first host and the third and fourth submission queues are managed by the second host, processing a command from the selected submission queue, and updating the aggregated value table based on a weight value corresponding to the processed command from among the first and second weights and input/output (I/O) information of the processed command.

    Memory controller and storage device including the same

    公开(公告)号:US11200000B2

    公开(公告)日:2021-12-14

    申请号:US16799213

    申请日:2020-02-24

    Abstract: A storage device includes a memory device including a plurality of memory cells respectively storing data having a plurality of bits, and a memory controller including an operation block including a plurality of unit circuits executing a predetermined function, and a core block executing a control operation on the plurality of memory cells in response to a command from a host. The core block selects at least portions of the plurality of unit circuits to determine selection unit circuits, and generates a control command specifying an operation order of the selection unit circuits. In the operation block, the selection unit circuits operate by the operation order to determine a control voltage required for the control operation, and store the control voltage in at least one of the memory controller or the memory device.

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