公开(公告)号：US20210134372A1

公开(公告)日：2021-05-06

申请号：US16676023

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

公开(公告)号：US20210134370A1

公开(公告)日：2021-05-06

申请号：US16701450

申请日：2019-12-03

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

公开(公告)号：US10984867B1

公开(公告)日：2021-04-20

申请号：US16724876

申请日：2019-12-23

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Sarath Chandran Puthen Thermadam ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

Abstract: A memory apparatus and method of operation are provided. The apparatus includes first memory cells coupled to control circuit and a particular word line and storing a first cell data. The apparatus also includes second memory cells coupled to a source side neighbor word line disposed on a source side of the particular word line and storing second cell threshold voltages programmed after the first cell data. The control circuit senses the second cell threshold voltages at a first time while applying a predetermined initial read voltage to the source side neighbor word line. The control circuit senses the first cell data at a second time while iteratively applying one of a plurality of particular read voltages to the particular word line and simultaneously and iteratively applying one of a plurality of neighbor pass voltages to the source side neighbor word line based on the second cell threshold voltages.

公开(公告)号：US10910075B2

公开(公告)日：2021-02-02

申请号：US16189200

申请日：2018-11-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US10811089B2

公开(公告)日：2020-10-20

申请号：US16829888

申请日：2020-03-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

公开(公告)号：US10726922B2

公开(公告)日：2020-07-28

申请号：US16000237

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/08 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  H01L27/1157 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/24

Abstract: Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.

公开(公告)号：US20200152282A1

公开(公告)日：2020-05-14

申请号：US16189200

申请日：2018-11-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US10482985B2

公开(公告)日：2019-11-19

申请号：US16017996

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  H01L27/1157 ,  G11C11/56

Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.

公开(公告)号：US20170309344A1

公开(公告)日：2017-10-26

申请号：US15640563

申请日：2017-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Arash Hazeghi ,  Huai-Yuan Tseng ,  Cynthia Hsu ,  Navneeth Kankani

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

公开(公告)号：US12051467B2

公开(公告)日：2024-07-30

申请号：US16892753

申请日：2020-06-04

Applicant: SanDisk Technologies LLC

Inventor： Huai-Yuan Tseng ,  Henry Chin ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.