公开(公告)号：US20170309752A1

公开(公告)日：2017-10-26

申请号：US15488626

申请日：2017-04-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Ryo TOKUMARU ,  Yasumasa YAMANE ,  Kiyofumi OGINO ,  Taichi ENDO ,  Hajime KIMURA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L27/105

CPC classification number: H01L29/78606 ,  H01L27/1052 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film. The source and drain electrodes each includes a conductive oxide film in contact with the oxide semiconductor film. The conductive oxide film has more oxygen vacancies than the oxide semiconductor film.

公开(公告)号：US20170288064A1

公开(公告)日：2017-10-05

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/46 ,  H01L29/66 ,  H01L21/425

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US20170278975A1

公开(公告)日：2017-09-28

申请号：US15474082

申请日：2017-03-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Yutaka OKAZAKI

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78696

Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10−5 Ω·m or more and 4.8×10−3 Ω·m or less.

公开(公告)号：US20170110588A1

公开(公告)日：2017-04-20

申请号：US15389846

申请日：2016-12-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Yukinori SHIMA ,  Hajime TOKUNAGA ,  Toshinari SASAKI ,  Keisuke MURAYAMA ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78606 ,  H01L21/02109 ,  H01L21/02263 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.

公开(公告)号：US20160284856A1

公开(公告)日：2016-09-29

申请号：US15077029

申请日：2016-03-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihisa SHIMOMURA ,  Tetsuhiro TANAKA ,  Masayuki KIMURA ,  Ryo TOKUMARU ,  Daisuke MATSUBAYASHI ,  Yasumasa YAMANE

IPC: H01L29/786 ,  G02F1/1368 ,  H01L27/32 ,  H01L29/24 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/78603

Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a first insulator, a second insulator, a semiconductor, and a conductor. The semiconductor is over the first insulator. The second insulator is over the semiconductor. The conductor is over the second insulator. The semiconductor includes a first region, a second region, and a third region. The first region is a region where the semiconductor overlaps with the conductor. Each of the second region and the third region is a region where the semiconductor does not overlap with the conductor. The second region and the third region each have a region with a spinel crystal structure.

Abstract translation: 提供了包括小型化晶体管的半导体器件。 半导体器件包括第一绝缘体，第二绝缘体，半导体和导体。 半导体在第一绝缘体之上。 第二绝缘体在半导体上。 导体在第二绝缘体之上。 半导体包括第一区域，第二区域和第三区域。 第一区域是半导体与导体重叠的区域。 第二区域和第三区域中的每一个都是半导体不与导体重叠的区域。 第二区域和第三区域各自具有尖晶石晶体结构的区域。

公开(公告)号：US20160218106A1

公开(公告)日：2016-07-28

申请号：US15090674

申请日：2016-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke MATSUBAYASHI

IPC: H01L27/105 ,  H01L29/16 ,  H01L29/78 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/105 ,  H01L27/0629 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/78 ,  H01L29/7869

Abstract: The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor. The other of the source and drain electrodes of the second transistor is electrically connected to the first wiring, and a gate electrode of the second transistor is electrically connected to one of electrodes of a second capacitor and a fifth wiring. The other electrode of the first capacitor is electrically connected to a third wiring, and the other electrode of the second capacitor is eclectically connected to a fourth wiring.

Abstract translation: 本发明的半导体器件包括第一和第二晶体管以及第一和第二电容器。 第一晶体管的源极和漏极之一电连接到第一布线，另一个电连接到第二布线，并且第一晶体管的栅电极电连接到源电极和漏电极中的一个 第二晶体管和第一电容器的电极中的一个。 第二晶体管的源极和漏极中的另一个电连接到第一布线，并且第二晶体管的栅电极电连接到第二电容器的电极和第五布线之一。 第一电容器的另一个电极电连接到第三布线，第二电容器的另一个电极折叠地连接到第四布线。

公开(公告)号：US20150109019A1

公开(公告)日：2015-04-23

申请号：US14516096

申请日：2014-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinpei MATSUDA ,  Toshihiko TAKEUCHI ,  Daisuke MATSUBAYASHI

IPC: G01R31/26 ,  G01R27/26

CPC classification number: G01R31/2621 ,  H01L22/14 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: A method for evaluating a buried channel in a semiconductor device including a semiconductor layer having a stacked-layer structure is provided. A method for evaluating a semiconductor device is provided, which includes the steps of: electrically short-circuiting a source and a drain of a transistor; applying DC voltage and AC voltage to a gate to obtain a CV characteristic that indicates a relationship between the DC voltage and a capacitance between the gate and each of the source and the drain; and determining that a semiconductor layer of the transistor includes a stacked-layer structure, when the capacitance in a region in an accumulation state in the CV characteristic is increased stepwise.

Abstract translation: 提供了一种用于评估包括具有堆叠层结构的半导体层的半导体器件中的掩埋沟道的方法。 提供了一种用于评估半导体器件的方法，其包括以下步骤：使晶体管的源极和漏极电短路; 将DC电压和AC电压施加到栅极以获得指示DC电压与栅极与源极和漏极之间的电容之间的关系的CV特性; 并且当所述CV特性中的累积状态区域中的电容逐步增加时，确定所述晶体管的半导体层包括堆叠层结构。

公开(公告)号：US20140138676A1

公开(公告)日：2014-05-22

申请号：US14079898

申请日：2013-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Hiroyuki MIYAKE

IPC: H01L29/786 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/045 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78627 ,  H01L29/78696

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, a semiconductor film overlapping with the gate electrode with the gate insulating film positioned therebetween, a source electrode and a drain electrode that are in contact with the semiconductor film, and an oxide film over the semiconductor film, the source electrode, and the drain electrode. An end portion of the semiconductor film is spaced from an end portion of the source electrode or the drain electrode in a region overlapping with the semiconductor film in a channel width direction. The semiconductor film and the oxide film each include a metal oxide including In, Ga, and Zn. The oxide film has an atomic ratio where the atomic percent of In is lower than the atomic percent of In in the atomic ratio of the semiconductor film.

Abstract translation: 提供了一种高度可靠的半导体器件。 半导体器件包括栅电极，栅电极上的栅极绝缘膜，与栅电极重叠的半导体膜，栅绝缘膜位于其间，与半导体膜接触的源电极和漏极，以及 半导体膜上的氧化膜，源电极和漏电极。 半导体膜的端部与沟道宽度方向上与半导体膜重叠的区域与源电极或漏电极的端部隔开。 半导体膜和氧化膜各自包括包含In，Ga和Zn的金属氧化物。 氧化物膜具有原子比，其中In的原子百分比低于In的原子百分比，以半导体膜的原子比计。

公开(公告)号：US20130181214A1

公开(公告)日：2013-07-18

申请号：US13738443

申请日：2013-01-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO. ,Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Yutaka OKAZAKI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78696

Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10−5 Ω·m or more and 4.8×10−3 Ω·m or less.

Abstract translation: 半导体器件包括具有沟道形成区域的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管。 在晶体管中，沟道长度小（5nm以上且小于60nm，优选为10nm以上且40nm以下），栅极绝缘膜的厚度大（通过以下方式获得的等效氧化物厚度 转化成含有氮的氧化硅的厚度为5nm以上且50nm以下，优选为10nm以上至40nm以下。 或者，沟道长度小（5nm以上且小于60nm，优选为10nm以上且40nm以下），源区域和漏极区域的电阻率为1.9×10 -5Ω·m 以上4.8×10 -3Ω·m以下。

公开(公告)号：US20240355930A1

公开(公告)日：2024-10-24

申请号：US18626777

申请日：2024-04-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuya HANAOKA ,  Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI ,  Shunpei YAMAZAKI ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/785 ,  H01L29/7854

Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.