公开(公告)号：US20150311074A1

公开(公告)日：2015-10-29

申请号：US14734492

申请日：2015-06-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Yuichi SATO ,  Kosei NODA

IPC: H01L21/02

CPC classification number: H01L29/66477 ,  H01L21/02565 ,  H01L21/265 ,  H01L29/66969 ,  H01L29/7869

Abstract: An oxide semiconductor film is formed over a substrate. A sacrifice film is formed to such a thickness that the local maximum of the concentration distribution of an injected substance injected into the oxide semiconductor film in the depth direction of the oxide semiconductor film is located in a region from an interface between the substrate and the oxide semiconductor film to a surface of the oxide semiconductor film. Oxygen ions are injected as the injected substance into the oxide semiconductor film through the sacrifice film at such an acceleration voltage that the local maximum of the concentration distribution of the injected substance in the depth direction of the oxide semiconductor film is located in the region, and then the sacrifice film is removed. Further, a semiconductor device is manufactured using the oxide semiconductor film.

Abstract translation: 在基板上形成氧化物半导体膜。 牺牲膜形成为使得在氧化物半导体膜的深度方向上注入到氧化物半导体膜中的注入物质的浓度分布的局部最大值位于从衬底和氧化物之间的界面的区域中的局部最大值 半导体膜到氧化物半导体膜的表面。 将氧离子作为注入物质通过牺牲膜以这样的加速电压注入到氧化物半导体膜中，使得注入物质在氧化物半导体膜的深度方向上的浓度分布的局部最大值位于该区域中，以及 然后去除牺牲膜。 此外，使用氧化物半导体膜制造半导体器件。

公开(公告)号：US20150053975A1

公开(公告)日：2015-02-26

申请号：US14501965

申请日：2014-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Mizuho SATO ,  Mitsuhiro ICHIJO ,  Toshiya ENDO

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

Abstract translation: 在具有栅极结构的晶体管中，栅电极层与其间插入有栅极绝缘层的沟道区域的氧化物半导体层重叠，当绝缘层中含有大量的氢时，氢扩散 由于绝缘层与氧化物半导体层接触，所以进入氧化物半导体层; 因此，晶体管的电特性降低。 本发明的目的是提供一种具有良好电特性的半导体器件。 与形成沟道区域的氧化物半导体层接触的绝缘层使用其氢浓度小于6×1020原子/ cm3的绝缘层。 使用绝缘层，可以防止氢的扩散，并且可以提供具有良好电特性的半导体器件。

公开(公告)号：US20140011319A1

公开(公告)日：2014-01-09

申请号：US14013383

申请日：2013-08-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Mizuho SATO

IPC: H01L29/66

CPC classification number: H01L21/02554 ,  H01L21/02488 ,  H01L21/02664 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract translation: 使用含有硅氧化物自由基的绝缘层作为与用于形成沟道的氧化物半导体层接触的绝缘层。 氧从绝缘层释放，由此可以减少氧化物半导体层中的氧缺乏和绝缘层与氧化物半导体层之间的界面状态。 因此，可以制造可靠性高，电特性变化小的半导体装置。

公开(公告)号：US20130344650A1

公开(公告)日：2013-12-26

申请号：US14010574

申请日：2013-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei NODA

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L27/1156 ,  H01L27/1207 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes an oxide semiconductor film including a pair of first regions, a pair of second regions, and a third region; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode provided between the pair of electrodes with the gate insulating film interposed therebetween. The pair of first regions overlap with the pair of electrodes, the third region overlaps with the gate electrode, and the pair of second regions are formed between the pair of first regions and the third region. The pair of second regions and the third region each contain nitrogen, phosphorus, or arsenic. The pair of second regions have a higher element concentration than the third region.

Abstract translation: 半导体器件包括包括一对第一区域，一对第二区域和第三区域的氧化物半导体膜; 与氧化物半导体膜接触的一对电极; 氧化物半导体膜上的栅极绝缘膜; 以及设置在所述一对电极之间的栅电极，其间插入有所述栅极绝缘膜。 所述一对第一区域与所述一对电极重叠，所述第三区域与所述栅电极重叠，并且所述一对第二区域形成在所述一对第一区域与所述第三区域之间。 一对第二区域和第三区域各自含有氮，磷或砷。 一对第二区域具有比第三区域更高的元件浓度。

公开(公告)号：US20130175530A1

公开(公告)日：2013-07-11

申请号：US13733536

申请日：2013-01-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei NODA ,  Yuta ENDO

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L27/1255 ,  H01L29/04 ,  H01L29/785 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a fin-type transistor having an oxide semiconductor in a channel formation region in which the channel formation region comprising an oxide semiconductor is three-dimensionally structured and a gate electrode is arranged to extend over the channel formation region. Specifically, the fin-type transistor comprises: an insulator protruding from a substrate plane; an oxide semiconductor film extending beyond the insulator; a gate insulating film over the oxide semiconductor film; and a gate electrode over and extending beyond the oxide semiconductor film. This structure allows the expansion of the width of the channel formation region, which enables the miniaturization and high integration of a semiconductor device having the transistor. Additionally, the extremely small off-state current of the transistor contributes to the formation of a semiconductor device with significantly reduced power consumption.

Abstract translation: 提供了在通道形成区域中具有氧化物半导体的翅片型晶体管，其中包括氧化物半导体的沟道形成区域是三维构造的，并且栅电极被布置成在沟道形成区域上延伸。 具体地，鳍型晶体管包括：从基板平面突出的绝缘体; 延伸超过绝缘体的氧化物半导体膜; 氧化物半导体膜上的栅极绝缘膜; 以及在氧化物半导体膜之上并延伸超过氧化物半导体膜的栅电极。 这种结构允许扩大通道形成区域的宽度，这使得能够使具有晶体管的半导体器件的小型化和高集成化。 此外，晶体管的非常小的截止状态电流有助于形成具有显着降低的功耗的半导体器件。

公开(公告)号：US20230064813A1

公开(公告)日：2023-03-02

申请号：US17980693

申请日：2022-11-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  G09G3/20 ,  G09G3/3291 ,  H01L29/786 ,  H03K19/003 ,  H03K19/096 ,  G11C19/28 ,  H03K17/16 ,  G09G3/36 ,  G11C19/18

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

公开(公告)号：US20210296371A1

公开(公告)日：2021-09-23

申请号：US17340165

申请日：2021-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  G09G3/20 ,  G09G3/3291 ,  H01L29/786 ,  H03K19/003 ,  H03K19/096 ,  G11C19/28 ,  H03K17/16 ,  G09G3/36 ,  G11C19/18

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

公开(公告)号：US20200212078A1

公开(公告)日：2020-07-02

申请号：US16816806

申请日：2020-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  G11C19/18 ,  G09G3/36 ,  H03K17/16 ,  G11C19/28 ,  G09G3/20 ,  H03K19/096 ,  H03K19/003 ,  H01L29/786 ,  G09G3/3291

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

公开(公告)号：US20200176608A1

公开(公告)日：2020-06-04

申请号：US16787562

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L29/786 ,  H01L27/02 ,  H01L27/12

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

公开(公告)号：US20190088785A1

公开(公告)日：2019-03-21

申请号：US16121700

申请日：2018-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  H01L29/26 ,  H01L23/66 ,  H01L27/12 ,  H01L27/088 ,  G06K19/077 ,  H01L29/66 ,  H01L29/24 ,  H01L21/8236 ,  G11C7/00 ,  G11C19/28 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.