公开(公告)号：US11233512B2

公开(公告)日：2022-01-25

申请号：US17017494

申请日：2020-09-10

Applicant: SK hynix Inc.

Inventor： Jin Ha Hwang ,  Yo Han Jeong ,  Eun Ji Choi

IPC: H03K19/0185 ,  H03K19/20 ,  G11C7/10 ,  H03K19/08

Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

公开(公告)号：US11158356B1

公开(公告)日：2021-10-26

申请号：US17097948

申请日：2020-11-13

Applicant: SK hynix Inc.

Inventor： Jin Ha Hwang ,  Kwan Su Shon ,  Keun Seon Ahn ,  Yo Han Jeong ,  Eun Ji Choi

IPC: G11C5/14 ,  G11C7/10

Abstract: Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.

公开(公告)号：US11100960B2

公开(公告)日：2021-08-24

申请号：US16733881

申请日：2020-01-03

Applicant: SK hynix Inc.

Inventor： Kwan Su Shon ,  Dong Hyun Kim ,  Yo Han Jeong

IPC: G11C7/10 ,  G11C5/14 ,  G11C8/18 ,  G11C8/10

Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.

公开(公告)号：US10742181B2

公开(公告)日：2020-08-11

申请号：US16164187

申请日：2018-10-18

Applicant: SK hynix Inc.

Inventor： Dong Hyun Kim ,  Eun Ji Choi ,  Yo Han Jeong ,  Jae Heung Kim

IPC: H03F3/45 ,  G11C7/10 ,  H03K19/0185

Abstract: A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.

公开(公告)号：US10284156B2

公开(公告)日：2019-05-07

申请号：US15668097

申请日：2017-08-03

Applicant: SK hynix Inc.

Inventor： Dong Hyun Kim ,  Eun Ji Choi ,  Yo Han Jeong ,  Soon Ku Kang ,  Woo Jin Kang ,  Kwan Su Shon ,  Hyun Bae Lee ,  Tae Jin Hwang

IPC: H03F3/45 ,  G05F1/565 ,  H03M1/00

Abstract: An amplifier may include a differential pair circuit configured to generate an output signal according to a first input signal and a second input signal, a plurality of current sinks coupled between a ground terminal and the differential pair circuit, and a feedback circuit configured to sense a level of the output signal and generate a feedback signal. At least one of the plurality of current sinks is controlled according to the feedback signal.

公开(公告)号：US09948298B2

公开(公告)日：2018-04-17

申请号：US15377225

申请日：2016-12-13

Applicant: SK hynix Inc.

Inventor： Yo Han Jeong

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  H03K17/687

CPC classification number: H03K19/0005 ,  H03K17/687

Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.

公开(公告)号：US09787506B2

公开(公告)日：2017-10-10

申请号：US14986177

申请日：2015-12-31

Applicant: SK hynix Inc.

Inventor： Kwan Su Shon ,  Yo Han Jeong

IPC: H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03267 ,  H04L25/03146 ,  H04L25/063

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.