公开(公告)号：US20210384241A1

公开(公告)日：2021-12-09

申请号：US17326537

申请日：2021-05-21

Applicant: STMicroelectronics Pte Ltd

Inventor： Laurent HERARD ,  David GANI

IPC: H01L27/146

Abstract: A digital image sensor package includes an image sensor substrate and a glass covering. The image sensor substrate carries photodiodes. The glass covering has a bottom surface, a top surface opposite the bottom surface, and a sidewall delimiting a perimeter edge of the glass covering. The glass covering overlies the photodiodes. A surface area of the top surface of the glass covering is greater than a surface area of the bottom surface of the glass covering such that the sidewall is anti-perpendicular to the top and bottom surfaces of the glass.

公开(公告)号：US20210202419A1

公开(公告)日：2021-07-01

申请号：US17104968

申请日：2020-11-25

Applicant: STMICROELECTRONICS PTE LTD

Inventor： David GANI

IPC: H01L23/00 ,  H01L23/498

Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP to reduce failures that may result from the WLCSP being exposed to thermal cycling or the WLCSP being dropped.

公开(公告)号：US20210159136A1

公开(公告)日：2021-05-27

申请号：US17145028

申请日：2021-01-08

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yun LIU ,  David GANI

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304 ,  H01L23/28

Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.

公开(公告)号：US20210035952A1

公开(公告)日：2021-02-04

申请号：US16935081

申请日：2020-07-21

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong CHEN ,  David GANI

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/16 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00

Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

公开(公告)号：US20200168582A1

公开(公告)日：2020-05-28

申请号：US16692720

申请日：2019-11-22

Applicant: STMicroelectronics Pte Ltd ,  STMicroelectronics (Grenoble 2) SAS

Inventor： David GANI ,  Jean-Michel RIVIERE

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/48 ,  H01L23/528

Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.

公开(公告)号：US20170186644A1

公开(公告)日：2017-06-29

申请号：US14982103

申请日：2015-12-29

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Laurent HERARD ,  David GANI

IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/561 ,  H01L21/565 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/85

Abstract: A method for making at least one integrated circuit (IC) package includes positioning an electrically conductive shield layer adjacent an interior of a mold, and coupling the mold onto a substrate carrying at least one IC thereon. A molding material is supplied into the interior of the mold to form an encapsulated body over the at least one IC and substrate with the electrically conductive shield layer at an outer surface of the encapsulated body.

公开(公告)号：US20170110618A1

公开(公告)日：2017-04-20

申请号：US14885215

申请日：2015-10-16

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Laurent HERARD ,  David GANI

IPC: H01L31/167 ,  H01L33/00 ,  H01L31/0203 ,  H01L33/54 ,  H01L31/18 ,  H01L33/58

CPC classification number: H01L31/167 ,  G01D5/34715 ,  G01S7/481 ,  G01S7/4813 ,  G01S17/026 ,  H01L25/167 ,  H01L31/0203 ,  H01L31/16 ,  H01L31/18 ,  H01L33/005 ,  H01L33/54 ,  H01L33/58 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/15151 ,  H01L2924/1815 ,  H01L2933/005 ,  H01L2933/0058

Abstract: An electronic device includes a substrate, an optical sensor coupled to the substrate, and an optical emitter coupled to the substrate. A lens is aligned with the optical emitter and includes an upper surface and an encapsulation bleed stop groove around the upper surface. An encapsulation material is coupled to the substrate and includes first and second encapsulation openings therethrough aligned with the optical sensor and the lens, respectively.