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公开(公告)号：US20160284920A1
公开(公告)日：2016-09-29
申请号：US14671707
申请日：2015-03-27
Inventor： Eric SAUGIER , Wing Shenq WONG , David GANI
CPC classification number: H01L31/167 , H01L25/167 , H01L31/02005 , H01L31/18 , H01L2224/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01S5/02248 , H01S5/0226 , H01S5/02276 , H01S5/183 , H01L2924/00014 , H01L2924/00
Abstract: A proximity sensor having a relatively small footprint includes a substrate, a semiconductor die, a light emitting device, and a cap. The light emitting device overlies the semiconductor die. The semiconductor die is secured to the substrate and includes a sensor area capable of detecting light from by the light emitting device. The cap also is secured to the substrate and includes a light barrier that prevents some of the light emitted by the light emitting device from reaching the sensor area. In one embodiment, the light emitting device and the semiconductor die are positioned on the same side of the substrate, wherein the light emitting device is positioned on the semiconductor die. In another embodiment, the light emitting device is positioned on one side of the substrate and the semiconductor die is positioned on an opposing side of the substrate.
Abstract translation: 具有相对较小占地面积的接近传感器包括衬底，半导体管芯，发光器件和帽。 发光器件覆盖半导体管芯。 半导体管芯被固定到基板上并且包括能够检测来自发光器件的光的传感器区域。 盖子也被固定到基板上并且包括防止由发光装置发射的一些光到达传感器区域的光栅。 在一个实施例中，发光器件和半导体管芯位于衬底的相同侧上，其中发光器件位于半导体管芯上。 在另一个实施例中，发光器件位于衬底的一侧，并且半导体管芯位于衬底的相对侧上。
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公开(公告)号：US20190319157A1
公开(公告)日：2019-10-17
申请号：US16378153
申请日：2019-04-08
Inventor： Romain COFFY , Laurent HERARD , David GANI
IPC: H01L31/12 , H01L31/0203
Abstract: A carrier wafer has a back face and a front face and a network of electrical connections between the back face and the front face. A first electronic chip is mounted with its bottom face on top of the front face of the carrier wafer. The first electronic chip has a through-opening extending between the bottom face and a face. A second electronic chip is installed in the through-opening and mounted to the front face of the carrier wafer.
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公开(公告)号：US20200168582A1
公开(公告)日：2020-05-28
申请号：US16692720
申请日：2019-11-22
Inventor： David GANI , Jean-Michel RIVIERE
IPC: H01L25/065 , H01L23/498 , H01L23/48 , H01L23/528
Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.
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公开(公告)号：US20220122941A1
公开(公告)日：2022-04-21
申请号：US17483076
申请日：2021-09-23
Applicant: STMicroelectronics PTE LTD
Inventor： Chun Yi TENG , David GANI
IPC: H01L23/00 , H01L21/768 , H01L21/78
Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.
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公开(公告)号：US20210327863A1
公开(公告)日：2021-10-21
申请号：US17360925
申请日：2021-06-28
Applicant: STMICROELECTRONICS PTE LTD
Inventor： David GANI
IPC: H01L25/16 , G01S17/04 , H01S5/02325 , H01L21/768 , H01L23/48 , H01L31/02 , H01L31/167 , H01L31/18 , H04M1/02
Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.
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Patent Agency Ranking
公开(公告)号：US20200241068A1
公开(公告)日：2020-07-30
申请号：US16746201
申请日：2020-01-17
Applicant: STMicroelectronics Pte Ltd
Inventor： Pedro Jr Santos PERALTA , David GANI
IPC: G01R31/28 , G01R31/26 , G01R31/3185 , H01L21/66
Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.
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公开(公告)号：US20190195685A1
公开(公告)日：2019-06-27
申请号：US16213197
申请日：2018-12-07
Applicant: STMICROELECTRONICS PTE LTD
Inventor： Laurent HERARD , David GANI
CPC classification number: G01J1/0271 , G01J1/4204
Abstract: One or more embodiments are directed to ambient light sensor packages, and methods of making ambient light sensor packages. One embodiment is directed to an ambient light sensor package that includes an ambient light sensor die having opposing first and second surfaces, a light sensor on the first surface of the ambient light sensor die, one or more conductive bumps on the second surface of the ambient light sensor die, and a light shielding layer on at least the first surface and the second surface of the ambient light sensor die. The light shielding layer defines an opening over the light sensor. The ambient light sensor package may further include a transparent cover between the first surface of the ambient light sensor die and the light shielding layer, and an adhesive that secures the transparent cover to the ambient light sensor die.
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公开(公告)号：US20240194709A1
公开(公告)日：2024-06-13
申请号：US18582860
申请日：2024-02-21
Applicant: STMicroelectronics PTE LTD
Inventor： Laurent HERARD , David GANI
IPC: H01L27/146
CPC classification number: H01L27/14618
Abstract: Disclosed herein is a method of reducing noise captured by an image sensor. The method includes affixing a bottom surface of a glass covering to the image sensor, permitting light to impinge upon the glass covering, and shaping the glass covering such that when the light that impinges upon the glass covering impinges upon a sidewall of the glass covering, the sidewall reflects the light on a trajectory away from the image sensor.
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公开(公告)号：US20230197688A1
公开(公告)日：2023-06-22
申请号：US18166931
申请日：2023-02-09
Applicant: STMICROELECTRONICS PTE LTD
Inventor： Yong CHEN , David GANI
IPC: H01L25/065 , H01L23/00 , H01L21/56 , H01L23/498 , H01L25/16 , H01L23/13
CPC classification number: H01L25/0657 , H01L24/05 , H01L21/565 , H01L21/563 , H01L23/49866 , H01L25/16 , H01L23/13 , H01L24/32 , H01L23/49816 , H01L2224/05009 , H01L2225/06503 , H01L2224/32225
Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.
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公开(公告)号：US20220291277A1
公开(公告)日：2022-09-15
申请号：US17826705
申请日：2022-05-27
Applicant: STMicroelectronics Pte Ltd
Inventor： Pedro Jr Santos PERALTA , David GANI
IPC: G01R31/28 , H01L21/66 , G01R31/3185 , G01R31/26
Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.
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