公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US20240014215A1

公开(公告)日：2024-01-11

申请号：US18343298

申请日：2023-06-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Villaret ,  Olivier Weber ,  Franck Arnaud

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L29/7838 ,  H01L21/84

Abstract: A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region.

公开(公告)号：US20180269115A1

公开(公告)日：2018-09-20

申请号：US15897003

申请日：2018-02-14

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Emmanuel Richard ,  Olivier Weber

IPC: H01L21/84 ,  H01L29/51 ,  H01L27/12 ,  H01L21/28

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/51

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

公开(公告)号：US09929146B2

公开(公告)日：2018-03-27

申请号：US15454788

申请日：2017-03-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L29/732 ,  H01L21/84 ,  H01L21/8249 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US09876032B2

公开(公告)日：2018-01-23

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L21/336 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

公开(公告)号：US20150041900A1

公开(公告)日：2015-02-12

申请号：US14309385

申请日：2014-06-19

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier Weber ,  Nicolas Planes ,  Rossella Ranica

IPC: H01L27/12 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/78648

Abstract: The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg−0.04−0.005*Xge

Abstract translation: 本发明涉及包括半导体衬底和第一和第二单元的集成电路。 每个单元包括nMOS和pMOS型的第一和第二晶体管，包括包括栅极金属的第一和第二栅极堆叠。 在第一和第二晶体管之下有第一和第二接地层，以及在晶体管和接地层之间延伸的氧化物层。 nMOS和pMOS的栅极金属表现出第一功函数，另一个pMOS的栅极金属表现出大于第一功函数的第二功函数。 工作函数之间的差异在55和85meV之间，第一功函数Wf1满足关系Wfmg-0.04-0.005 * Xge