公开(公告)号：US20230411332A1

公开(公告)日：2023-12-21

申请号：US18340380

申请日：2023-06-23

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/49816

Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

公开(公告)号：US20230030627A1

公开(公告)日：2023-02-02

申请号：US17812679

申请日：2022-07-14

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: B81B7/00 ,  B81C1/00 ,  H01S5/02255 ,  H01S5/02345 ,  H01S5/0236

Abstract: Provided is a sensor package with an integrated circuit embedded in a substrate and a sensor die on the substrate. The substrate includes a molding compound that has additives configured to respond to a laser. The integrated circuit is embedded in the molding compound. An opening is through the substrate and is aligned with the sensor die. A lid covers the sensor die and the substrate, forming a cavity. At least one trace is formed on a first surface of the substrate, on an internal sidewall of the opening and on a second surface of the substrate with a laser direct structuring process.

公开(公告)号：US20220189788A1

公开(公告)日：2022-06-16

申请号：US17513122

申请日：2021-10-28

Applicant: STMicroelectronics Pte Ltd

Inventor： Jing-En LUAN

IPC: H01L21/48 ,  H01L23/498 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01S5/02315 ,  H01S5/02345 ,  H01S5/02218

Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

公开(公告)号：US20210395077A1

公开(公告)日：2021-12-23

申请号：US17344576

申请日：2021-06-10

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: B81B7/00 ,  B81C1/00

Abstract: The present disclosure is directed to a package (e.g., a chip scale package, a wafer level chip scale package (WLCSP), or a package containing a sensor die) with a sensor die on a substrate (e.g., an application-specific integrated circuit die (ASIC), an integrated circuit, or some other type of die having active circuitry) and encased in a molding compound. The sensor die includes a sensing component that is aligned with a centrally located opening that extends through the substrate. The centrally located opening extends through the substrate at an inactive portion of the substrate. The centrally located opening exposes the sensing component of the sensor die to an external environment outside the package.

公开(公告)号：US20210080547A1

公开(公告)日：2021-03-18

申请号：US17015521

申请日：2020-09-09

Applicant: STMicroelectronics PTE LTD

Inventor： Jing-En LUAN

IPC: G01S7/481

Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.

公开(公告)号：US20180331236A1

公开(公告)日：2018-11-15

申请号：US16027647

申请日：2018-07-05

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN ,  Laurent HERARD ,  Yong Jiang LEI

IPC: H01L31/0203 ,  H01L31/153 ,  H01L31/18 ,  H01L31/12 ,  G01S7/481

CPC classification number: H01L31/0203 ,  G01S7/481 ,  G01S7/4813 ,  G01S17/026 ,  G01S17/46 ,  H01L25/50 ,  H01L31/125 ,  H01L31/153 ,  H01L31/173 ,  H01L31/18

Abstract: One or more embodiments are directed to system in package (SiP) for optical devices, such as proximity sensing or optical ranging devices. One embodiment is directed to an optical sensor package that includes a substrate, a sensor die coupled to the substrate, a light-emitting device coupled to the substrate, and a cap. The cap is positioned around side surfaces of the sensor die and covers at least a portion of the substrate. The cap includes first and second sidewalls, an inner wall having first and second side surfaces and a mounting surface, and a cover in contact with the first and second sidewalls and the inner wall. The first and second side surfaces are transverse to the mounting surface, and the inner wall includes an opening extending into the inner wall from the mounting surface. A first adhesive material is provided on the sensor die and at least partially within the opening, and secures the inner wall to the sensor die.

公开(公告)号：US20230245992A1

公开(公告)日：2023-08-03

申请号：US18081248

申请日：2022-12-14

Applicant: STMicroelectronics PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/822 ,  H01L21/56

CPC classification number: H01L24/24 ,  H01L23/49805 ,  H01L21/822 ,  H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/19 ,  H01L2224/24226 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/73209 ,  H01L2224/16227 ,  H01L2924/182

Abstract: An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.

公开(公告)号：US20230029799A1

公开(公告)日：2023-02-02

申请号：US17874052

申请日：2022-07-26

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/31 ,  H01L27/146

Abstract: The present disclosure is directed to embodiments of sensor package including a doped resin on respective surfaces and sidewalls of a transparent portion, a sensor die, and a support structure extending from the transparent portion to the sensor die. The support structure suspends the transparent portion over a sensor of the sensor die. The doped resin is doped with an additive material, and the additive material is activated by exposing the doped resin to a laser. The doped resin is exposed to the laser forming conductive layers extending along the doped resin for providing electrical connections within the sensor package and to electronic components external to the embodiments of the sensor die packages. The conductive layers are at least partially covered by a non-conductive layer.

公开(公告)号：US20220352133A1

公开(公告)日：2022-11-03

申请号：US17714822

申请日：2022-04-06

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.

公开(公告)号：US20220285256A1

公开(公告)日：2022-09-08

申请号：US17677505

申请日：2022-02-22

Applicant: STMicroelectronics Pte Ltd

Inventor： Jing-En LUAN

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A method of forming a wafer-level package includes singulating a wafer into a plurality of reconstituted integrated circuit dice, affixing a carrier to a front side of the plurality of integrated circuit dice, and forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dice, over side edges of the plurality of integrated circuit die, and over adjacent portions of the carrier. Desired areas of the LDS activatable resin are activated to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die.