公开(公告)号：US10002672B2

公开(公告)日：2018-06-19

申请号：US15795552

申请日：2017-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C7/00 ,  G11C16/28 ,  G11C16/32 ,  G11C16/26 ,  G11C11/56 ,  G11C8/14 ,  G11C8/08 ,  G11C7/22 ,  G11C7/14 ,  G11C16/24 ,  G11C16/08 ,  G11C7/06

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/14 ,  G11C7/227 ,  G11C8/08 ,  G11C8/14 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.

公开(公告)号：US09865356B2

公开(公告)日：2018-01-09

申请号：US15275362

申请日：2016-09-24

Applicant: STMicroelectronics S.r.l

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2207/12

Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

公开(公告)号：US20170263323A1

公开(公告)日：2017-09-14

申请号：US15275362

申请日：2016-09-24

Applicant: STMicroelectronics S.r.l

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2207/12

Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

公开(公告)号：US20170062055A1

公开(公告)日：2017-03-02

申请号：US15140770

申请日：2016-04-28

Applicant: STMicroelectronics S.r.l

Inventor： Salvatore Polizzi ,  Giovanni Campardo

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

Abstract translation: 非易失性存储器件包括具有以字线布置并接收电源电压的存储器单元的存储器阵列。 行解码器包括输入和预解码模块，其被配置为在电源电压范围内接收地址信号并产生低电压的预解码地址信号。 驱动模块被配置为产生偏置信号，用于在高电压和高于电源的升压电压的范围内从作为预解码地址信号的函数的解码的地址信号开始偏置存储器阵列的字线 电压。 处理模块被配置为接收预解码的地址信号，并共同执行逻辑组合的操作和用于生成解码的地址信号的预解码的地址信号的升压的操作。