公开(公告)号：US20230163182A1

公开(公告)日：2023-05-25

申请号：US18094484

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L29/792 ,  H01L29/511 ,  H01L29/517 ,  H01L2924/0002

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US11588032B2

公开(公告)日：2023-02-21

申请号：US17129667

申请日：2020-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20230044895A1

公开(公告)日：2023-02-09

申请号：US17969022

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20210111260A1

公开(公告)日：2021-04-15

申请号：US17129667

申请日：2020-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20200258994A1

公开(公告)日：2020-08-13

申请号：US16859437

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L29/51 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/06 ,  H01L21/3213

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20180191481A1

公开(公告)日：2018-07-05

申请号：US15901093

申请日：2018-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

IPC: H04L5/00 ,  H04L1/18

CPC classification number: H04L5/0091 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926 ,  H04L1/1812

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

公开(公告)号：US20130171744A1

公开(公告)日：2013-07-04

申请号：US13715099

申请日：2012-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-HOON KANG ,  Taegon Kim ,  Hanmei Choi ,  Eunyoung Jo ,  Gonsu Kang ,  Sungho Kang ,  Sungho Heo

IPC: H01L21/324

CPC classification number: H01L21/324 ,  H01L21/67115 ,  H01L21/67288 ,  H01L21/681 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract translation: 一种热处理晶片的方法包括将晶片装载到具有一个或多个均匀温度梯度区域和一个或多个不均匀温度梯度区域的处理室中。 在晶片中检测到缺陷。 将晶片对准以将缺陷定位在均匀温度梯度的一个或多个区域之一内。 在处理室中的晶片上执行快速热处理，同时将缺陷定位在均匀温度梯度的一个或多个区域之一内。