公开(公告)号：US20230094440A1

公开(公告)日：2023-03-30

申请号：US17956443

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomwoo GU ,  Jaeseok PARK ,  Jaehyun PARK ,  Youngho RYU ,  Jungkyu HAN

IPC: H02J50/12 ,  H03H1/00

Abstract: According to various embodiments, an example wireless power transmitter may include a transistor configured to output an amplified signal based on an input signal and a driving voltage, a first capacitor coupled to the transistor in parallel, a first LC resonant circuit coupled to the transistor in parallel and including a first inductor and a second capacitor coupled to the first inductor in series, a third capacitor having a first end coupled to an output terminal of the transistor and the first LC resonant circuit, a feeding coil coupled to a second end of the third capacitor in series, and having at least a part configured to form a second LC resonant circuit with the third capacitor, and a transmission resonator including a transmission coil and a fourth capacitor coupled to the transmission coil in series. At least a part of the transmission coil may be magnetically coupled with the feeding coil, and at least a part of power received from the feeding coil may be output to an outside through the transmission resonator.

公开(公告)号：US20230040473A1

公开(公告)日：2023-02-09

申请号：US17970216

申请日：2022-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomwoo GU ,  Jaeseok PARK ,  Jaehyun PARK ,  Jaesun SHIN ,  Jihyun YANG ,  Jeongman LEE ,  Seogyong JEONG ,  Hyoseok HAN

IPC: H02J7/00 ,  H02J50/12 ,  H02J7/34 ,  H02J50/80

Abstract: An electronic device may include: a resonance circuit which comprises a battery, a coil and a capacitor, and receives power wirelessly; a rectifier which rectifies AC power, provided from the resonance circuit, to DC power; a DC/DC converter which converts and outputs the DC power provided from the rectifier; a charger which charges the battery by using the converted power provided from the DC/DC converter; a first OVP circuit which selectively connects the coil to the capacitor; a second OVP circuit which is connected in parallel to the first OVP circuit; a detection circuit which detects a rectified voltage; a control circuit; and a communication circuit, wherein the control circuit, on the basis that the detected rectified voltage is equal to or greater than a first threshold voltage, controls the first OVP circuit so as to be in an off state so that the coil is not connected to the capacitor, and on the basis that the detected rectified voltage is less than a second threshold voltage, controls the first OVP circuit so that the first OVP circuit is switched from the off state to an on state so that the coil is connected to the capacitor, wherein the second threshold voltage may be smaller than the first threshold voltage.

公开(公告)号：US20220374693A1

公开(公告)日：2022-11-24

申请号：US17876136

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

Inventor： Yuhwan RO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC: G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F17/16 ,  G06F9/38 ,  G06F9/30

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

公开(公告)号：US20220209930A1

公开(公告)日：2022-06-30

申请号：US17469062

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanseok KIM ,  Hobin SONG ,  Jaehyun PARK

IPC: H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03L7/093

Abstract: A clock data recovery circuit includes a phase locked loop (PLL), a code signal generator, and a clock and data generator. The PLL generates a plurality of reference clock signals of which frequencies are modulated. Each of the plurality of reference clock signals has a first profile that is periodically fluctuated. The code signal generator generates a first compensation code signal. The first compensation code signal has a second profile that is periodically fluctuated and is different from the first profile. The clock and data generator generates a recovered data signal by sampling an input data signal based on a clock signal, compensates a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and includes a phase interpolator that generates the clock signal based on the plurality of reference clock signals and the first compensation code signal.

公开(公告)号：US20220200605A1

公开(公告)日：2022-06-23

申请号：US17503802

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsuk JANG ,  Hanseok KIM ,  Jaehyun PARK ,  Hobin SONG ,  Jongshin SHIN ,  Youngjin CHUNG

IPC: H03L7/08 ,  H03L7/081 ,  H04L1/20 ,  H04L1/00

Abstract: An integrated circuit may include a receiver configured to receive a first data signal based on an mth (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.

公开(公告)号：US20210143677A1

公开(公告)日：2021-05-13

申请号：US16889214

申请日：2020-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbong LEE ,  Beomwoo GU ,  Jaehyun PARK ,  Sanghyuk WI

IPC: H02J50/12 ,  H02J50/80 ,  H02P27/08 ,  H02M7/48

Abstract: A wireless power transmitter may include: a power factor correction (PFC) circuit configured to convert first alternating current (AC) power input from a power source into direct current (DC) power; an inverter configured to convert the DC power output from the PFC circuit into second AC power; a power transmission circuit configured to transmit wireless power, based on the second AC power output from the inverter; and at least one processor configured to identify at least one of a voltage or a current of the DC power output from the PFC circuit, and control an operation of the inverter based on the identified at least one of the voltage or the current

公开(公告)号：US20200374604A1

公开(公告)日：2020-11-26

申请号：US16876376

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungbum PARK ,  Kyungwoo LEE ,  Jaehyun PARK ,  Sungku YEO ,  Jeongman LEE

IPC: H04Q9/00 ,  G01R21/133 ,  H02J50/00 ,  H02J50/10

Abstract: A sensor device is provided. The sensor device includes an energy harvester configured to generate electric energy, a monitoring circuit, a sensor, a communication circuit, and at least one processor configured to obtain information indicating a magnitude of the generated electric energy via the monitoring circuit, obtain a sensing value via the sensor, and transmit the sensing value and the information indicating the magnitude of the generated electric energy via the communication circuit to the other electronic device.

公开(公告)号：US20250062888A1

公开(公告)日：2025-02-20

申请号：US18934842

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun KIM ,  Nakwon LEE ,  Jaehyun PARK ,  Kyeongjoon KO ,  Kangjik KIM ,  Seuk SON ,  Byunghyun LIM

IPC: H04L7/00

Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

公开(公告)号：US20240356444A1

公开(公告)日：2024-10-24

申请号：US18368339

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dam YUN ,  Jaehyun PARK ,  Jehyung YOON ,  Sangik CHO

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M1/009

Abstract: A bi-directional direct current to direct current (DC-DC) converter includes: an inductor; a first switching transistor configured to switch a power supply voltage to one end of the inductor, in response to a first driving signal; a second switching transistor configured to switch between one end of the inductor and a ground voltage, in response to a second driving signal; and a bi-directional current sensor configured to sense a bi-directional current flowing through the second switching transistor in a boost mode and a buck mode, based on a switching node voltage at a drain of the second switching transistor, wherein the bi-directional current sensor is further configured to generate a virtual voltage of a positive voltage in a negative feedback method regardless of the sign of the switching node voltage to copy the bi-directional current.

公开(公告)号：US20230335557A1

公开(公告)日：2023-10-19

申请号：US18136464

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil PARK ,  Jaehyun PARK

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0922 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7831

Abstract: A semiconductor device includes a first common source/drain and a second common source/drain spaced apart from each other in a first direction; a first channel structure between the first common source/drain and the second common source/drain, and a second channel structure between the first common source/drain and the second common source/drain and spaced apart from the first channel structure in a vertical direction; a first gate structure surrounding an upper surface, a lower surface, and side surfaces of the first channel structure; and a second gate structure surrounding an upper surface, a lower surface, and side surfaces of the second channel structure, and spaced apart from the first gate structure, wherein a level of the second channel structure is higher than a level of the first channel structure.