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公开(公告)号:US20250062240A1
公开(公告)日:2025-02-20
申请号:US18611488
申请日:2024-03-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: MyungDo Cho , Youngchan Ko , Byung Ho Kim , Yongkoon Lee , Jeongho Lee
IPC: H01L23/538 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
Abstract: An example semiconductor package includes a first redistribution layer, a bridge chip attached to a top surface of the first redistribution layer, a mold layer on the first redistribution layer and enclosing the bridge chip, a second redistribution layer disposed on the mold layer, a conductive post extending through the mold layer vertically and connecting the first redistribution layer and the second redistribution layer, and a first semiconductor chip mounted on the second redistribution layer. The first redistribution layer includes a pad layer and an interconnection layer disposed on the pad layer. The pad layer includes a first insulating layer and pads in the first insulating layer. Top surfaces of the pads are exposed to an outside of a top surface of the first insulating layer, and bottom surfaces of the pads are exposed to an outside of a bottom surface of the first insulating layer.
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公开(公告)号:US12205939B2
公开(公告)日:2025-01-21
申请号:US17501108
申请日:2021-10-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Doohwan Lee , Seokhyun Lee , Jeongho Lee
IPC: H01L25/18 , H01L23/498 , H01L23/538 , H01L25/065
Abstract: A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.
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公开(公告)号:US12056066B2
公开(公告)日:2024-08-06
申请号:US17466726
申请日:2021-09-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeongho Lee , Younho Jeon , Daehui Kim , Heehyun Nam
CPC classification number: G06F13/1668 , G06F13/4022
Abstract: A device configured to communicate through a bus may include a first interface circuit configured to, based on a first protocol, provide first access to a first memory through the bus and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus. The second interface circuit may be configured to access the first memory in response to a message received through the bus based on the second protocol to provide second access to the first memory through the bus.
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公开(公告)号:US11979119B2
公开(公告)日:2024-05-07
申请号:US17250748
申请日:2019-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunchul Park , Byungjoon Park , Daehyun Kang , Juho Son , Sunggi Yang , Jeongho Lee , Yunsung Cho
Abstract: Disclosed is a 5G (5th generation) or pre-5G communication system for supporting a data transmission rate higher than that of a 4G (4th generation) communication system such as long-term evolution (LTE). A transmission device comprises: a first amplification unit having a common source structure, including cross coupled capacitors, and amplifying an input signal; a second amplification unit, having a common gate structure, for amplifying a signal output from the first amplification unit; and a first removal unit which is connected to output terminals of the first amplification unit and input terminals of the second amplification unit and which removes at least one portion of second harmonics. The first removal unit can offset, with respect to a fundamental frequency, at least some of parasitic capacitance generated from the output terminals of the first amplification unit and the input terminals of the second amplification unit, and can ground a signal having a secondary harmonic frequency with respect to the secondary harmonic frequency.
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公开(公告)号:US11973042B2
公开(公告)日:2024-04-30
申请号:US17867388
申请日:2022-07-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jingu Kim , Shanghoon Seo , Sangkyu Lee , Jeongho Lee
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/538
CPC classification number: H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L2221/68372 , H01L2224/214 , H01L2924/3511
Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post' and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.
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公开(公告)号:US11899970B2
公开(公告)日:2024-02-13
申请号:US17742184
申请日:2022-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseb Jeong , Hee Hyun Nam , Younggeon Yoo , Jeongho Lee , Younho Jeon , Ipoom Jeong , Chanho Yoon
IPC: G06F3/06
CPC classification number: G06F3/0658 , G06F3/0611 , G06F3/0622 , G06F3/0683
Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.
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公开(公告)号:US11809341B2
公开(公告)日:2023-11-07
申请号:US17378354
申请日:2021-07-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeongho Lee , Ipoom Jeong , Younggeon Yoo , Younho Jeon
CPC classification number: G06F13/1668 , G06F3/061 , G06F3/065 , G06F3/0673
Abstract: A method performed by a device connected to a host processor via a bus includes: providing a first read request including a first address to a memory; receiving a second address stored in a first region of the memory corresponding to the first address, from the memory; providing a second read request including the second address to the memory; and receiving first data stored in a second region of the memory corresponding to the second address, from the memory, wherein the first read request further includes information indicating that the first address is an indirect address of the first data.
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公开(公告)号:US11659070B2
公开(公告)日:2023-05-23
申请号:US17466742
申请日:2021-09-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Younho Jeon , Hyeokjun Choe , Jeongho Lee
Abstract: An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.
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公开(公告)号:US11283532B2
公开(公告)日:2022-03-22
申请号:US16725323
申请日:2019-12-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jooseok Lee , Jeongho Lee , Juho Son
Abstract: A communication method and a system for converging a 4th-Generation (4G) communication system or a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The disclosure provides an electronic device including a wireless communication module. The wireless communication module includes an antenna array including at least one antenna element, a phase shifter configured to control a phase of a beam radiating from the antenna array, a processor electrically connected to the phase shifter and configured to perform beamforming by controlling the phase shifter, and a memory including phase offset information of the wireless communication module.
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30.
公开(公告)号:US11171415B2
公开(公告)日:2021-11-09
申请号:US16177767
申请日:2018-11-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeongho Lee , Dae Young Lee , Sunggi Yang
IPC: H01Q3/00 , H01Q3/26 , H01Q3/34 , H04B7/06 , H03K21/38 , H04B17/14 , H04L5/00 , H04B7/00 , H04L7/00
Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). An electronic device including a first radio frequency (RF) chip and a second RF chip is provided. The electronic device includes a modem configured to transmit a first clock signal to the second RF chip, the first RF chip connected to the modem and configured to receive a second clock signal from the modem, and the second RF chip electrically connected to the first RF chip through a transmission line and configured to receive the second clock signal from the first RF chip and to measure a phase of the transmission line based on the first clock signal and the second clock signal. The first clock signal and the second clock signal have different frequencies.
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