公开(公告)号：US20230059169A1

公开(公告)日：2023-02-23

申请号：US17718795

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dongmyoung Kim ,  Cheol Kim ,  Dongsuk Shin ,  Woogwan Shim ,  Seung Hun Lee ,  Soonwook Jung

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.

公开(公告)号：US20230051750A1

公开(公告)日：2023-02-16

申请号：US17689322

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ingyu Jang ,  Jinbum Kim ,  Dahye Kim ,  Sujin Jung ,  Dongsuk Shin

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/764 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

公开(公告)号：US20230006052A1

公开(公告)日：2023-01-05

申请号：US17656023

申请日：2022-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： HAEJUN YU ,  Kyungin Choi ,  Sungmin Kim ,  Seunghun Lee ,  Jinbum Kim

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device includes first and second channels, first and second gate structures, first and second source/drain layers, first and second fin spacers, and first and second etch stop patterns. The first channels are disposed vertically on a first region of a substrate. The second channels are disposed vertically on a second region of the substrate. The first gate structure is formed on the first region and covers the first channels. The second gate structure is formed on the second region and covers the second channels. The first and second source/drain layers contact the first and second channels, respectively. The first and second fin spacers contact sidewalls and upper surfaces of the first and second source/drain layers, respectively. The first and second etch stop patterns are formed on the first and second fin spacers, respectively, and do not contact the first and second source/drain layers, respectively.

公开(公告)号：US20250092522A1

公开(公告)日：2025-03-20

申请号：US18669753

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim

IPC: C23C16/46 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52 ,  H01L21/02

Abstract: A semiconductor processing apparatus includes a support configured to support a wafer, a chamber including an upper dome and a lower dome, a facility cover that at least partially surrounds the chamber, a pre-heating unit that is below the support and is configured to heat the wafer, an upper lamp that is on the chamber and is configured to heat the wafer, a first process gas supply unit configured to supply a first process gas to the chamber, a second process gas supply unit configured to supply a second process gas to the chamber, a valve that is between the second process gas supply unit and the chamber, a pump that is connected to the chamber and is configured to discharge gas from the chamber, and a control unit, where the pre-heating unit includes a first lamp that is different from the upper lamp.

公开(公告)号：US12256566B2

公开(公告)日：2025-03-18

申请号：US17714450

申请日：2022-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim

IPC: H10D64/23 ,  H10D30/01 ,  H10D30/67 ,  H10D64/01

Abstract: A semiconductor device includes an active pattern on a substrate, source/drain patterns on the active pattern, a plurality of channel layers stacked on the active pattern to be vertically spaced apart from each other and connecting the source/drain patterns with each other, a gate electrode between the source/drain patterns to cross the active pattern and to surround the channel layers, and active contacts at opposite sides of the gate electrode to cover top surfaces of the source/drain patterns. A width of each of the active contacts is smaller than or equal to the largest width of each of the source/drain patterns. Each of the top surfaces of the source/drain patterns has an inclined surface that is inclined relative to a top surface of the substrate, and each of the active contacts includes a protruding portion that protrudes toward the inclined surface.

公开(公告)号：US12256564B2

公开(公告)日：2025-03-18

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H10D62/13 ,  H10D30/60 ,  H10D30/67 ,  H10D30/69 ,  H10D62/822 ,  H10D64/01 ,  H10D64/23 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US12178034B2

公开(公告)日：2024-12-24

申请号：US18501576

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Youngjun Kim ,  Jinbum Kim

IPC: H10B12/00

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US20240321991A1

公开(公告)日：2024-09-26

申请号：US18503019

申请日：2023-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingeon Hwang ,  Jinbum Kim ,  Hyojin Kim ,  Sangmoon Lee ,  Yongjun Nam ,  Taehyung Lee

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region on a substrate, a nanosheet on a fin top surface of the fin-type active region, the nanosheet being apart from the fin top surface of the fin-type active region in a vertical direction, a gate line surrounding the nanosheet on the fin-type active region, and a source/drain region on the fin-type active region, the source/drain region being in contact with the nanosheet, wherein the nanosheet includes a multilayered sheet comprising a first outer semiconductor sheet, a core semiconductor sheet, and a second outer semiconductor sheet, which are sequentially stacked in the vertical direction.

公开(公告)号：US12046682B2

公开(公告)日：2024-07-23

申请号：US17689322

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ingyu Jang ,  Jinbum Kim ,  Dahye Kim ,  Sujin Jung ,  Dongsuk Shin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

公开(公告)号：US20230411458A1

公开(公告)日：2023-12-21

申请号：US18239660

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.