公开(公告)号：US11882696B2

公开(公告)日：2024-01-23

申请号：US17558884

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonsung Choi ,  Jinwoo Park

IPC: G11C17/16 ,  H10B20/20 ,  G11C17/14 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18

Abstract: A one-time programmable (OTP) memory device includes an access transistor, a word line, a voltage line, a well, a first filling oxide layer, a first semiconductor layer, and a bit line. The access transistor includes a gate structure on a substrate, and first and second impurity regions at portions of the substrate adjacent to the gate structure. The word line is electrically connected to the gate structure. The voltage line is electrically connected to the first impurity region. The well is formed at an upper portion of the substrate, and is doped with impurities having a first conductivity type. The first filling oxide layer is formed on the well. The first semiconductor layer is formed on the first filling oxide layer, and is doped with impurities having the first conductivity type and electrically connected to the second impurity region. The bit line is electrically connected to the well.

公开(公告)号：US11373716B2

公开(公告)日：2022-06-28

申请号：US16804470

申请日：2020-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wandong Kim ,  Jinwoo Park ,  Seongjin Kim ,  Sang-wan Nam

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/12 ,  G11C7/10 ,  G11C16/24

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

公开(公告)号：US11367493B2

公开(公告)日：2022-06-21

申请号：US16991443

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wandong Kim ,  Jinwoo Park ,  Seongjin Kim ,  Sang-Wan Nam

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C7/10 ,  G11C16/04 ,  G11C7/04 ,  G11C16/30

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

公开(公告)号：US11243562B2

公开(公告)日：2022-02-08

申请号：US16487600

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinman Kim ,  Suna Kim ,  Joohan Kim ,  Jinwoo Park ,  Hunjo Jung ,  Eunyeung Lee ,  Hyunsuk Choi

IPC: G06K9/00 ,  G06F1/16 ,  G06F21/32

Abstract: Various embodiments of the present invention relate to an electronic device comprising a biometric sensor disposed in a display, and the electronic device comprises: a transparent cover; a display module located under the transparent cover, wherein the display module comprises a display layer in which pixels are formed and one or more additional layers formed under the display layer, and an opening is formed in at least a partial region of at least one layer among the one or more layers; a first printed circuit board having a biometric sensor module, which is disposed under the display module and makes contact with the opening; and a second printed circuit board electrically connected to the first printed circuit board and the display module, wherein a pressure sensor module can be disposed in the surrounding region of the biometric sensor module under the display module in the second printed circuit board. In addition, other embodiments are possible.

公开(公告)号：US20210367121A1

公开(公告)日：2021-11-25

申请号：US17154632

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inho KIM ,  Yongmin Kwon ,  Sanghyun Kim ,  Jinwoo Park ,  Dongyeoul Lee ,  Dongju Lee ,  Sangbum Lee ,  Jonghyun Lee ,  Dahyun Choi

IPC: H01L33/62 ,  H01L27/15 ,  H01L33/22 ,  H01L33/38 ,  H01L33/46 ,  H01L33/50 ,  H01L33/58 ,  H01L33/64

Abstract: A light source module includes a light-emitting cell, a wiring structure provided on the light-emitting cell and connected to the light-emitting cell, a support structure that is apart from the light-emitting cell with the wiring structure therebetween in a vertical direction, a printed circuit board (PCB) that is apart from the wiring structure with the support substrate therebetween in the vertical direction and overlapping the light-emitting cell in the vertical direction, and at least one insulating film that is apart from the wiring structure in the vertical direction and covering at least one of a first surface of the support substrate, which faces the wiring structure, and a second surface of the support substrate, which faces the PCB.

公开(公告)号：US10026749B2

公开(公告)日：2018-07-17

申请号：US15349084

申请日：2016-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Jaeshin Park ,  Joyoung Park ,  Jiwoong Sue ,  Seok-Won Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend in the first direction on the first cell array region and are spaced apart from each other in a second direction crossing the first direction, an insulation layer that covers the stack structures, and at least one separation structure that extends in the second direction on the peripheral region and penetrates the insulation layer in a direction normal to a top surface of the substrate.

公开(公告)号：US20250167061A1

公开(公告)日：2025-05-22

申请号：US19029411

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US20250149494A1

公开(公告)日：2025-05-08

申请号：US18940264

申请日：2024-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekyung Yoo ,  Jinwoo Park ,  Kyonghwan Koh ,  Woohyeong Kim ,  Taeryong Kim

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip on an upper surface of the first substrate, a first bump between the first substrate and the first semiconductor chip, a first underfill layer that fills a center portion of a space between the first substrate and the first semiconductor chip, and a first molding member that covers an upper surface and side surfaces of the first semiconductor chip, and fills a periphery portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip.

公开(公告)号：US12277976B2

公开(公告)日：2025-04-15

申请号：US17941570

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun Yoon ,  Jinwoo Park

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/34

Abstract: Provided are a non-volatile memory device, a storage device including the same, and a method of performing a programming operation on the same. The method includes performing a program operation including applying a desired first program voltage to a selected word line of the memory device, the selected word line including a plurality of memory cells, performing a verification operation including sensing a first sensing value corresponding to an output of the selected word line based on a first verify voltage, and counting a number of on-cells of the selected word line based on the first sensing value to determine a first count value, determining whether a first program state of the selected word line has been verified based on the first count value and at least one reference value, and setting a second program voltage based on results of the determining whether the first program state has been verified.

公开(公告)号：US20240387168A1

公开(公告)日：2024-11-21

申请号：US18624788

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Heeyeop Chae ,  Yongjae Kim ,  Sangwuk Park ,  Yuna Lee ,  Jihye Lee ,  Jungpyo Hong

IPC: H01L21/02 ,  C23C16/44 ,  H01L21/311

Abstract: A method of manufacturing a semiconductor element includes placing a structure, the structure including a substrate and a first metal-containing film disposed on the substrate, fluorinating at least one atomic layer from an exposed surface of the first metal-containing film by supplying a fluorinating gas to the structure to form a fluorinated atomic layer, and etching the fluorinated atomic layer of the first metal-containing film by supplying an etching gas to the structure, wherein the etching gas includes an inert gas in a plasma state.