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    Semiconductor device
    21.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11101803B2

    公开(公告)日：2021-08-24

    申请号：US16820835

    申请日：2020-03-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejoong Song ,  Jungho Do ,  Seungyoung Lee ,  Jonghoon Jung

    IPC: H03K19/17724 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

    CELL ARCHITECTURE BASED ON MULTI-GATE VERTICAL FIELD EFFECT TRANSISTOR
    22.
    发明申请
    CELL ARCHITECTURE BASED ON MULTI-GATE VERTICAL FIELD EFFECT TRANSISTOR 审中-公开

    公开(公告)号：US20190386103A1

    公开(公告)日：2019-12-19

    申请号：US16257890

    申请日：2019-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092 ,  H01L23/522

    Abstract: A cell architecture is provided. A cell architecture including a vertical field effect transistor (VFET) having at least two fins serving as a vertical channel, a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing connection therebetween, and a top source/drain (S/D) including a first top S/D portion on the first fin and a second top S/D portion on the second fin, a gate contact structure connected to the third gate portion, a top S/D contact structure connected to one of the first top S/D portion or the second top S/D portion and serving as a horizontal conductive routing layer; and metal patterns on the gate contact structure and the top S/D contact structure and connected thereto through vias, and serving as a vertical conductive routing layer may be provided.

    Semiconductor devices
    23.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12159834B2

    公开(公告)日：2024-12-03

    申请号：US17532052

    申请日：2021-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

    INTEGRATED CIRCUIT INCLUDING MULTI-HEIGHT CELLS AND METHOD OF DESIGNING THE SAME
    26.
    发明公开
    INTEGRATED CIRCUIT INCLUDING MULTI-HEIGHT CELLS AND METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20230378156A1

    公开(公告)日：2023-11-23

    申请号：US18303607

    申请日：2023-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeongyu You ,  Jisu Yu ,  Geonwoo Nam ,  Jungho Do ,  Minjae Jeong ,  Jaehee Cho

    IPC: H01L27/02 ,  G06F30/31

    CPC classification number: H01L27/0207 ,  G06F30/31

    Abstract: An integrated circuit includes a first cell and a second cell respectively arranged in a first row and a second row that are adjacent to each other and extend in a first direction, and a third cell continuously arranged in the first row and the second row, wherein each of the first cell and the second cell comprises a first active pattern group including at least one active pattern that extends in the first direction and has a first conductivity type, the third cell comprises a second active pattern group including at least one active pattern that extends in the first direction in the first row and has the first conductivity type, and an effective channel width of the second active pattern group is greater than an effective channel width of the first active pattern group.

    Integrated circuit including cells of different heights and method of designing the integrated circuit
    27.
    发明授权
    Integrated circuit including cells of different heights and method of designing the integrated circuit 有权

    公开(公告)号：US11727184B2

    公开(公告)日：2023-08-15

    申请号：US17877483

    申请日：2022-07-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bonghyun Lee ,  Jungho Do

    IPC: G06F30/00 ,  G06F30/392 ,  H01L23/528 ,  H01L27/02

    CPC classification number: G06F30/392 ,  H01L23/5286 ,  H01L27/0207

    Abstract: An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.

    Integrated circuit including cells of different heights and method of designing the integrated circuit
    29.
    发明授权
    Integrated circuit including cells of different heights and method of designing the integrated circuit 有权

    公开(公告)号：US11494544B2

    公开(公告)日：2022-11-08

    申请号：US17183630

    申请日：2021-02-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bonghyun Lee ,  Jungho Do

    IPC: G06F30/00 ,  G06F30/392 ,  H01L27/02 ,  H01L23/528

    Abstract: An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.

    Semiconductor device
    30.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11323119B2

    公开(公告)日：2022-05-03

    申请号：US17088819

    申请日：2020-11-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejoong Song ,  Jungho Do ,  Seungyoung Lee ,  Jonghoon Jung

    IPC: H03K19/17724 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

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