公开(公告)号：US12249558B2

公开(公告)日：2025-03-11

申请号：US18341087

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jubin Seo ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park ,  Sujeong Park ,  Jaewon Hwang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

公开(公告)号：US11961788B2

公开(公告)日：2024-04-16

申请号：US17708137

申请日：2022-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoukyung Cho ,  Hojin Lee ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0649 ,  H01L2225/06544

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure. The first front side interconnection layer is on a level higher than that of the conductive line.

公开(公告)号：US20240038732A1

公开(公告)日：2024-02-01

申请号：US18487247

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/08 ,  H01L2224/08146

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US11887966B2

公开(公告)日：2024-01-30

申请号：US17376784

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam Kim ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06541

Abstract: A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

公开(公告)号：US11804419B2

公开(公告)日：2023-10-31

申请号：US17185166

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Kwangjin Moon ,  Hyungjun Jeon ,  Hyoukyung Cho

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L25/0652 ,  H01L2224/08146

Abstract: A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.

公开(公告)号：US11791211B2

公开(公告)日：2023-10-17

申请号：US17691178

申请日：2022-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76898 ,  H01L21/02068 ,  H01L21/76831

Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

公开(公告)号：US11721628B2

公开(公告)日：2023-08-08

申请号：US16863126

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

公开(公告)号：US20220359348A1

公开(公告)日：2022-11-10

申请号：US17645472

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Hwang ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/485 ,  H01L23/535 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US11380607B2

公开(公告)日：2022-07-05

申请号：US17147927

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

公开(公告)号：US20210020543A1

公开(公告)日：2021-01-21

申请号：US16794782

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Kwangjin Moon ,  Eunji Kim ,  Taeseong Kim ,  Sangjun Park

IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.