公开(公告)号：US20220399228A1

公开(公告)日：2022-12-15

申请号：US17545468

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Minsu SEOL ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L21/768 ,  H01L23/532

Abstract: Disclosed are an interconnect structure, an electronic device including the same, and a method of manufacturing the interconnect structure. The interconnect structure includes a dielectric layer; a conductive interconnect on the dielectric layer; and a graphene cap layer on the conductive interconnect. The graphene cap layer contains graphene quantum dots, has a carbon content of 80 at % or more, and has an oxygen content of 15 at % or less.

公开(公告)号：US20220246718A1

公开(公告)日：2022-08-04

申请号：US17465213

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonchoo CHO ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Hyeonjin SHIN

IPC: H01L29/04 ,  H01L29/49 ,  H01L23/522 ,  H01L29/16 ,  H01L29/161

Abstract: A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

公开(公告)号：US20210206643A1

公开(公告)日：2021-07-08

申请号：US17138194

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Eunkyu LEE

IPC: C01B32/186 ,  C01B32/194 ,  C23C16/02 ,  C23C16/04 ,  C23C16/26 ,  C23C16/513

Abstract: Provided is a method of selectively growing graphene. The method includes forming an ion implantation region and an ion non-implantation region by implanting ions locally into a substrate; and selectively growing graphene in the ion implantation region or the ion non-implantation region.

公开(公告)号：US20250089320A1

公开(公告)日：2025-03-13

申请号：US18955290

申请日：2024-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonchoo CHO ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Hyeonjin SHIN

IPC: H01L29/04 ,  H01L23/522 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

公开(公告)号：US20240395613A1

公开(公告)日：2024-11-28

申请号：US18794736

申请日：2024-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sanghoon AHN ,  Woojin LEE ,  Kyung-Eun BYUN ,  Junghoo SHIN ,  Hyeonjin SHIN ,  Yunseong LEE

IPC: H01L21/768 ,  H01L21/285

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US20240038845A1

公开(公告)日：2024-02-01

申请号：US18335487

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minseok YOO ,  Minsu SEOL ,  Junyoung KWON ,  Kyung-Eun BYUN

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/1033 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/66431 ,  H01L29/41791

Abstract: A layer structure including a two-dimensional (2D) channel layer, a method of manufacturing a two-dimensional (2D) channel layer, an electronic device including the layer structure, and an electronic apparatus including the layer structure are disclosed. The layer structure may include a first substrate, a second substrate surrounded by the first substrate, and a 2D channel layer on the second substrate. An interfacial energy of the second substrate may be less than an interfacial energy of the first substrate. The method of manufacturing a 2D channel layer may include forming a second substrate to be surrounded by a first substrate, forming a precursor layer for forming a 2D channel on any one of the first and second substrates, and transforming the precursor layer into a liquid precursor layer. The interfacial energy of the second substrate may be less than the interfacial energy of the first substrate.

公开(公告)号：US20230238329A1

公开(公告)日：2023-07-27

申请号：US18158233

申请日：2023-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Joungeun YOO ,  Eunkyu LEE ,  Changseok LEE ,  Alum JUNG

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53276 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242

Abstract: An interconnect structure may include a dielectric layer including a trench, a conductive wiring including graphene filling an inside of the trench, and a liner layer in contact with at least one surface of the conductive wiring and including a metal.

公开(公告)号：US20230114933A1

公开(公告)日：2023-04-13

申请号：US17958653

申请日：2022-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Changseok LEE ,  Baekwon PARK

IPC: H01L21/02 ,  H01L23/532 ,  C23C16/40 ,  C23C16/455 ,  H01L21/768

Abstract: Provided are a graphene interconnect structure, an electronic device including the graphene interconnect structure, and a method of manufacturing the graphene interconnect structure. The graphene interconnect structure may include: a first oxide dielectric material layer; a second oxide dielectric material layer on a surface of the first oxide dielectric material layer and having a dielectric constant greater than that of the first oxide dielectric material layer; and a graphene layer on a surface of the second oxide dielectric material layer opposite to the surface on which the first oxide dielectric material layer is located.

公开(公告)号：US20230078018A1

公开(公告)日：2023-03-16

申请号：US17945534

申请日：2022-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Minseok YOO

IPC: H01L21/265 ,  H01L21/02 ,  C23C16/02 ,  C23C16/26

Abstract: Provided are a layer structure including a carbon-based material, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure may include a lower layer, an ion implantation layer in the lower layer, and a carbon-based material layer on the ion implantation layer, wherein the ion implantation layer includes carbon. The ion implantation layer may include a trench, and the carbon-based material layer may be provided in the trench. The carbon-based material layer may be formed to coat an inner surface of the trench. The carbon-based material layer may fill at least a portion of the trench. The ion implantation concentration of the ion implantation layer may be uniform as a whole. The ion implantation layer may have an ion implantation concentration gradient in a given direction.

公开(公告)号：US20230072229A1

公开(公告)日：2023-03-09

申请号：US17668004

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Sangwon KIM ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Eunkyu LEE

IPC: H01L27/108 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/76 ,  H01L29/786

Abstract: Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.