公开(公告)号：US09911644B2

公开(公告)日：2018-03-06

申请号：US15359724

申请日：2016-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wookyung You ,  Jongmin Baek ,  Sanghoon Ahn ,  Sangho Rha ,  Naein Lee

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

公开(公告)号：US09520300B2

公开(公告)日：2016-12-13

申请号：US14606970

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wookyung You ,  Jongmin Baek ,  Sanghoon Ahn ,  Sangho Rha ,  Naein Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US20150187699A1

公开(公告)日：2015-07-02

申请号：US14503877

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件包括导电图案之间的间隙。 此外，半导体器件在导电图案上包括可渗透层。 还提供了制造半导体器件的方法。

公开(公告)号：US08906761B2

公开(公告)日：2014-12-09

申请号：US13798700

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhye Kim ,  Sangho Rha ,  Jeong-Kyu Lee ,  Zulkarnain ,  Kyungseok Oh ,  Sangbom Kang ,  Seungjae Lee ,  Jungchan Lee

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device is manufactured using an expandable material. The method includes forming a first gate insulating layer on a substrate, forming first and second gate structures on the first gate insulating layer, the first and second gate structures being spaced apart from each other at a distance, forming an expandable material on sidewalls and upper surfaces of the first and second gate structures, forming a gap-fill layer on the expandable material between the first and second gate structures, and performing a heat-treatment process to increase the volume of the expandable material.

Abstract translation: 使用可膨胀材料制造半导体器件。 该方法包括在衬底上形成第一栅极绝缘层，在第一栅极绝缘层上形成第一和第二栅极结构，第一和第二栅极结构彼此间隔一定距离，在侧壁和上部形成可膨胀材料 第一和第二栅极结构的表面，在第一和第二栅极结构之间的可膨胀材料上形成间隙填充层，并且执行热处理工艺以增加可膨胀材料的体积。